myriadrf / limesdr-usb

USB 3.0 version of the LimeSDR board

LimeSDR

The LimeSDR board provides a hardware platform for developing and prototyping high-performance and logic-intensive digital and RF designs using Altera’s Cyclone IV FPGA and Lime Microsystems transceiver.

• USB Interface
  • Cypress FX3 super speed USB 3rd generation controller
• FPGA Features
  • Cyclone IV EP4CE40F23C8N device in 484-pin FPGA
  • 39’600 logic elements
  • 1134 Kbits embedded memory
  • 116 embedded 18x18 multipliers
  • 4 PLLs
• FPGA Configuration
  • JTAG mode configuration
  • Active serial mode configuration
  • Possibility to update FPGA gateware by using FX3 (USB)
• Memory Devices
  • 2x 1Gbit (64M x 16) DDR2 SDRAM
  • 4Mbit flash for FX3 firmware
  • 16Mbit flash for FPGA gateware
  • 3x 64K (8K x 8) EEPROMs for LMS MCU firmware, LMS MCU data and FX3 data
• Connections
  • 6-12V DC power jack
  • FPGA GPIO headers
  • Micro USB3.0 (type B) connector or USB3.0 (type A) plug
  • Coaxial RF (U.FL) connectors
• Clock System
  • 30.72MHz ±250 ppb on board VCTCXO
  • Possibility to lock VCTCXO to external clock or tune VCTCXO by onboard DAC
  • Programmable clock generator for the FPGA reference clock input or LMS PLLs
• Board Size 60mm x 100mm (2.36” x 3.94”)

Contents

The directory structure is as follows:

  fx3/                       - Cypress FX3 USB 3.0 controller firmware
     
  gateware/                  - Altera Cyclone IV FPGA project

  hardware/<variant>/<version>/
      Libraries/             - Component Libraries
      OutputJobs/            - Output jobs
      PCB/                   - PCB design
      Project Outputs/       - BOM, rule check reports, Gerbers, pick & place files, PDFs
      Schematics/            - Schematic diagrams

Revisions

The design databases published correspond to hardware revisions which have either gone into full production or been issued in limited number for testing in the community.

Please note that only certain versions of FPGA firmware and FX3 firmware will work with a given hardware revision. For further details see the FPGA and FX3 projects.

Associated projects

FPGA gateware

The FPGA gateware sources are located in the LimeSDR-USB_GW repository.

FX3 firmware

The Cypress FX3 USB 3.0 controller firmware sources are located in the LimeSDR-USB_FX3 repository.

Host driver

The host driver sources are located in the LimeSuite repository.

Licensing

The hardware designs are licensed under a Creative Commons Attribution 3.0 Unported licence.

limesdr-usb's Issues

Changed BOM and placement of parts

Does recent change of BOM and placement affect "connector" position? With connector position I mean: both USB versions, DC socket, LEDs, u.fl conn
Thank you for support!

Repository authority?

I'm guessing this repo is curated to be public-facing and doesn't represent whatever internal version control is being used in active development? The real thrust of my question is whether it's worth forking, contributing, and pull-requesting, or if this repository is going to be non-authoritative for the purpose of shielding intermediate development from the public. Are there plans to use this repo for active development in the future, or is it always likely to be a limited-commit public face?

TX/RX frequency range documentation

This isn't necessarily an issue, but for lack of a better place to discuss, I'll ask here: the LimeSDR is advertised with a working frequency range from 100kHz to 3.8GHz, but the schematic notes on the RF matching networks don't match this. I'm assuming (speaking of RX) that "RXRF2_L" is "low frequency", "_H" is "high frequency," and "_W" is "wideband." I suppose the overlap is to allow for mechanical design flexibility (using a single connection and antenna for full coverage) at the price of receive signal strength? Beyond that, both L+H and W seem to cover only 700MHz to 2.6GHz. Given my poor RF design skills, I don't know just looking at the matching networks if that's shorthand, or if those matching networks actually roll off sharply at those bounds and I'm missing something else. So I guess, what's the deal?

Duplicated channel naming in schematic

On 05_LMS7002M_RF.SchDoc, the note "TXRF1_A" is duplicated twice. On the left, it looks like it should be as-is, and on the right (IC1 Part 5/5, attached to pins pa1op_2 and pa1on_2) I think it should be TXRF1_B.

Confusing TX channel labeling

Each of the two TX channels has two independent power amplifiers, with independent outputs, feeding independent matching networks for high and low frequency range.

It makes most sense to me to number the mutually exclusive channels, and to letter the frequency divisions of them.

Specifically: (as-is name > proposed name)
TXRF1_A > TX1_L
TXRF1_B > TX2 _L
TXRF2_A > TX1_H
TXRF2_B > TX2_H

In fact, per current schematic, the net naming consistency seems poor - the channel noted "TXRF1_A" contains differential nets prefixed with "TXRF1," but so does the channel noted "TXRF2_A" right below it. This would be consistent with my "numbers for channels" convention requested above, but isn't consistent with the "letters for channels" convention currently in silk.

Android Support

How can I use the LimeSDR-USB with android tablet? Do you planned android driver? Because android tablets very powerful this days.

DDR reference plane

Not all DDR signals have continuous reference plane. Signals on layer L4 L8 L9 from DDR to FPGA are crossing split plane.

There are many references to that requirement:
4.1 http://www.ti.com/lit/an/spraaw8a/spraaw8a.pdf
25. http://www.nxp.com/files/32bit/doc/app_note/AN2910.pdf

Also clearance between polygon and DDR signals should be bigger.

EEPROM data missing

Hi, there are two EEPROM chips on LimeSDR USB board. I wasn't able to find the data to program those, where can it be sourced? Thanks

socket vs. plug naming

Please check that naming for folders match files:
1v2 -> plug -> micro USB 3.0 Type B
1v2s -> socket -> USB Type A

LimeSDR-USB/hardware/socket/1v2/Project Outputs for LimeSDR_1v2s/LimeSDR_1v2s_PCB_Drawings.PDF

BoM lists incorrect jack?

Was trying to figure out what external power supply to get, and looked in the BoM for the power jack so I could double-check my measurements.

The BoM at https://github.com/myriadrf/LimeSDR-USB/blob/master/hardware/plug/1v4/Project%20Outputs%20for%20LimeSDR-USB_1v4_LMS031pad/BOM/LimeSDR-USB_1v4_BOMr7.xls ( the -r4 version as well )

lists a 2.1x5.5mm power jack - however the mounting dimensions on it are much smaller than the plug it fits, so my guess is that somebody pasted the wrong information.

My device appears to have a 3.0x1.1mm jack

Can this get corrected?

Also, somebody should update the wiki with some guidance on the external power adapters so it's not so difficult to find.

Thanks

Lack of a mechanical drawing

Guys, please create a board mechanical drawing with the board and roles dimensions and distances.

A/D and D/A Enob?

A quick ctrl+f didn't gave me the information about the effective number of bits of the Digital<->Analog converters. Do you have this information somewhere?

Possibly cooked LimeSDR-USB

Hi myriadrf,

I think I may have killed a Lime by failing to connect a fan while leaving it running. LimeQuickTest shows the board as failed. Can you confirm that the below output would indicate a dead board, please? Also, if there’s a better place to ask this kind of question can you please point me in the right direction?

Thanks

Mike

sbc002:~$ LimeQuickTest
[ TESTING STARTED ]
->Start time: Fri Oct 25 12:44:11 2019

->Device: LimeSDR-USB, media=USB 3.0, module=FX3, addr=1d50:6108, serial=0009072C00D52D1D
Serial Number: 0009072C00D52D1D

[ Clock Network Test ]
->FX3 GPIF clock test
Test results: 31171; 34927; 38683 - PASSED
->Si5351C test
CLK0: 17554 / 17554 - PASSED
CLK1: 17554 / 17554 - PASSED
CLK2: 17554 / 17554 - PASSED
CLK3: 17554 / 17554 - PASSED
CLK4: 17554 / 17554 - PASSED
CLK5: 17554 / 17554 - PASSED
CLK6: 17554 / 17554 - PASSED
->ADF4002 Test
Result: 10 - PASSED
->VCTCXO test
Results : 5112924 (min); 5113070 (max) - PASSED
->Clock Network Test PASSED

[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 12 0C 06 12 0C 06 02
->FPGA EEPROM Test PASSED

[ LMS7002M Test ]
->Perform Registers Test
->External Reset line test
Reg 0x20: Write value 0xFFFD, Read value 0xFFFD
Reg 0x20: value after reset 0x0FFFF
->LMS7002M Test PASSED

[ RF Loopback Test ]
Note: The test should be run without anything connected to RF ports
->Configure LMS
->Run Tests (TX_2-> LNA_L):
SetFrequencySXR(800 MHz) - cannot deliver frequency
->Run Tests (TX_1 -> LNA_W):
SetFrequencySXR(1800 MHz) - cannot deliver frequency
->Run Tests (TX_2-> LNA_H):
SetFrequencySXR(2500 MHz) - cannot deliver frequency
->RF Loopback Test FAILED

=> Board tests FAILED <=

Elapsed time: 1.52 seconds

Could analog receive signals be provided or accessed?

Hi, myriadrf,

I want to access analog signals received by LimeSDR because of the requirement of higher signal resolution. Is it possible to doing this?

Thanks a lot for your help!

micro USB 3.0 Type B

BOM for hardware/plug/1v2 is valid from initial commit?
I already ordered micro usb connectors for my sample alu enclosure :)

If the LimeSDR can switch to the USB Type-C interface?

Hi, MyriadRF, this is Aaron.
Do you have any plans to upgrade the USB interface of LimeSDR?
USB Type-C port is now very common. It’s smaller, supports USB3.1 gen2 standard, and can provide faster transmission speed at the same time carry more current.
I think it's time to switch to the USB Type-C interface for LimeSDR.

The LimeSDR board is broken?

Hi, I wanna run OAI eNB use the board. Then I run the process, it aborted(core dump)! I checked it, shows:

and the leds(2 red and 2 yellow) beside USB port keep bright always! Who can tell me the reason and help me sovle the problem, Thanks a lot!