muratovas / icesugar-riscv

A RiscV verilog project for Lattice FPGA using VSCode. With the function of automated installation Toolchain

icesugar-riscv

FPGACode-ide -> IceSugar-riscv -> IceSugar-tv80 -> IceSugar-6502

Here you will find a project for IceSugar implementing RISCV32. As well as full automation of assembly and testing. More detailed documentation on usage in the FPGACode-ide.

This project is based on the developments of picorv32

What is done:

• RAM: SPRAM or BRAM
• ROM: BRAM or SPI FLASH
• UART: MiniUart or RingUart
• todo: SPI: Classic spi

Usage

The commands can be executed manually in the terminal as well as through the Task menu in Code

make all        #Project assembly
make synthesis  #Synthesis RTL
make flash      #Flash ROM
make prog       #Flash SRAM
make sim        #Perform Testbench
make formatter  #Perform code formatting
make build_fw   #Build firmware
make flash_fw   #Build firmware
make clean      #Cleaning the assembly of the project
make toolchain  #Install assembly tools

Using IceSugar resources

Info: Device utilisation:
Info:            ICESTORM_LC:  2468/ 5280    46%
Info:           ICESTORM_RAM:    20/   30    66%
Info:                  SB_IO:    11/   96    11%
Info:                  SB_GB:     8/    8   100%
Info:           ICESTORM_PLL:     0/    1     0%
Info:            SB_WARMBOOT:     0/    1     0%
Info:           ICESTORM_DSP:     0/    8     0%
Info:         ICESTORM_HFOSC:     1/    1   100%
Info:         ICESTORM_LFOSC:     0/    1     0%
Info:                 SB_I2C:     0/    2     0%
Info:                 SB_SPI:     0/    2     0%
Info:                 IO_I3C:     0/    2     0%
Info:            SB_LEDDA_IP:     0/    1     0%
Info:            SB_RGBA_DRV:     0/    1     0%
Info:         ICESTORM_SPRAM:     4/    4   100%