mou3ananya / prelayoutwork

This repository contains a structural as well as functional description of a comparator and a clock divider with 3.3v analog voltage and 1.8v digital voltage.This repository will maintain simulation files and other relevant files on the pre-mentioned design blocks worked on in the Online VSD IP Design Research Internship 2020

prelayoutWork

This repository contains a structural as well as functional description of a comparator and a clock divider with 3.3v analog voltage and 1.8v digital voltage. This repository will maintain simulation files and other relevant files on the pre-mentioned design blocks worked on in the Online VSD IP Design Research Internship program 2020.

Note: Circuit requires further optimization to improve performance. Design yet to be modified.

Table of contents

• Block Diagram of the Comparator IP
• Circuit Diagram of the Comparator IP
• Running the Simulation
• Pre-Layout Simulation
• Layout of Comparator
• Post-Layout Simulation
• Issues | Improvements | Future Work
• A Glance at the Clock Divider IP
• Block Diagram of the Clock Divider IP
• Circuit Diagram of the Clock Divider IP
• Running the Simulation
• Pre-Layout Simulation
• Layout of Comparator
• Post-Layout Simulation
• Issues | Improvements | Future Work
• Open-Source VLSI Tools
  • About Ngspice
  • About Magic
• Acknowledgments
• Contact Information

Block Diagram of the Comparator IP

CIRCUIT DIAGRAM of the Comparator IP

Running the Simulation

To enter the Ngspice Shell, open the terminal & type:

$ ngspice

To simulate a netlist, type:

ngspice 1 ->  source <filename>.cir

You can exit from the Ngspice Shell by typing:

ngspice 1 ->  exit

or

ngspice 1 ->  quit

Pre-Layout Simulation

To clone the Repository and download the Netlist files for Simulation, enter the following commands in your terminal.

$  sudo apt install -y git
$  git clone https://github.com/mou3ananya/prelayoutWork
$  cd prelayoutWork/comparator

Run the netlist file using the following command.

$  ngspice Comparator.cir

Vp:Non-inverting i/p terminal Vn:Inverting i/p terminal

Layout

Layout of Comparator

Post Layout Simulation

Issues | Improvements | Future Work

1. The biasing circuit is required some improvement in architecture since here I'm using 2Meg resister which is more area as well as power comsuming compare to MOS transister.
2. The current comparator can detect the difference between Vp(Non-inverting) and Vn(Inverting) i/p terminal voltage upto 20mv which needs an improvement upto 3.2mv to meet the specs of 10bit ADC IPhere.

Block Diagram of the Clock Divider IP

CIRCUIT DIAGRAM of the Clock Divider IP

Running the Simulation

To enter the Ngspice Shell, open the terminal & type:

$ ngspice

To simulate a netlist, type:

ngspice 1 ->  source <filename>.cir

You can exit from the Ngspice Shell by typing:

ngspice 1 ->  exit

or

ngspice 1 ->  quit

Pre-Layout Simulation

To clone the Repository and download the Netlist files for Simulation, enter the following commands in your terminal.

$  sudo apt install -y git
$  git clone https://github.com/mou3ananya/prelayoutWork
$  cd prelayoutWork/clkdivider

Run the netlist file using the following command.

$  ngspice CLK_Divider.cir

Layout

Layout of Clock Divider

Post Layout Simulation

Issues | Improvements | Future Work

Output pulse of the current clock divider is of 33% duty cycle since I've used one 3bit asynchronous up-counter followed by a MOD-3 asynchronous up counter. I'll modify the circuit to get 50% duty cycle which is important to meet the 10bit ADC IP spechere.

Open-Source VLSI Tools

About Ngspice

Ngspice is an open source mixed-signal circuit simulator.

Installing Ngspice

For Ubuntu

Open your terminal and type the following to install Ngspice

$  sudo apt-get install -y ngspice

Magic

Magic is a VLSI layout tool.

Type the following to install Magic in Ubuntu

$  wget http://opencircuitdesign.com/magic/archive/magic-8.3.54.tgz
$  tar xvfz magic-8.3.54.tgz
$  cd magic-8.3.54
$  ./configure
$  sudo make
$  sudo make install

Contributors

• Ananya Ghorai
• Kunal Ghosh

Acknowledgments

• Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
• Philipp Gühring, Software Architect, LibreSilicon Assocation

Contact Information

• Ananya Ghorai, Pursuing M.Tech in VLSI Design, IIT(ISM) Dhanbad, [email protected]
• Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. [email protected]
• Philipp Gühring, Software Architect, LibreSilicon Assocation [email protected]