mmahdi98 / systolicarrayconvolution

Implementation of Systolic Array Architecture for 2D Convolution, Designed by HT Kung et. al.

SystolicArrayConvolution

• Original Work is Done by H. T. Kung et al, here.
• You can see an overview of the architecture in file.
• The Original PE is implemented in serial bitwise style which is in serial_bitwise_pe.v file.
• The eight bit parallel or let's say 8bit serial version of PE, which uses a barrel shifter instead of a serial shifter, is in serial_8bit_pe.v file.
• 3x3 kernel, that is implemented in an 8bit approach.
• 5x5 kernel, 8bit too.
• 7x7 kernel, 8bit too.
• One of the challenging parts was implementing the multiplier which was used in the original design, you can see the schema of it in here

TODO

• Adding the schema of bitwise original design
• Adding the schema of 8bit serial design

for educational or scientific usage, please cite this repository