mikecovrado / core-v-mcu-uvm

CORE-V MCU UVM Environment and Test Bench

About

This project aims to bring the OpenHW Group's CORE-V MCU Project to TRL-5 and beyond via Advanced UVM Verification and the Moore.io libraries and toolchain. Datum and Low Power Futures are the primary contributors to this effort.

IP List

Name	Description
uvme_cvmcu_chip	CORE-V MCU Top-Level Environment
uvmt_cvmcu_chip	CORE-V MCU Top-Level Test Bench
uvme_apb_adv_timer_ss	APB Advanced Timer Sub-System Environment
uvme_apb_timer_ss	APB Timer Sub-System Environment
uvmt_apb_adv_timer_ss	APB Advanced Timer Sub-System Test Bench
uvmt_apb_timer_ss	APB Timer Sub-System Test Bench

Installing Toolchain

1. Create a free Moore.io IP Marketplace user account. The VIP libraries for this project are under license from Datum and credentials are needed to install them.
2. Install the Moore.io CLI Client: pipx install mio-cli
3. Download and install the latest version of Metrics DSim Cloud
4. Set an environment variable for the MDC installation location: export MIO_METRICS_HOME=/usr/local/bin
5. Download and install the latest version of Xilinx Vivado ML Edition
6. Set an environment variable for the Vivado installation location: export MIO_VIVADO_HOME=/path/to/vivado/bin

Supported Simulators

• Metrics DSim Cloud: 20230116.4.0
• Xilinx Vivado: 2022.2
• Siemens QuestaSim: ETA Q1 '23
• Synopsys VCS: ETA Q1 '23
• Cadence Xcelium: ETA Q1 '23
• Aldec Riviera-PRO: TBD

Getting the MCU RTL

The MCU RTL is included as a git submodule; if you do not clone the repository with --recursive, you will have to populate the submodule(s) manually:

git submodule update --init

Simulation

• The UVM libraries from Datum must first be installed:

mio install uvmt_cvmcu_chip

• To run compilation, elaboration and simulation for IP uvmt_cvmcu_chip, test reg_bit_bash, seed 1, high verbosity, with waveform capture enabled, using Metrics DSim Cloud simulator:

mio sim uvmt_cvmcu_chip -t reg_bit_bash -s 1 -v high -w -a mdc

• To run compilation, elaboration and simulation for IP uvmt_apb_timer_ss, test reg_hw_reset, seed 1, high verbosity, with waveform capture enabled, using the Vivado simulator:

mio sim uvmt_apb_timer_ss -t reg_hw_reset -s 1 -v high -w -a viv

Regressions

Running locally

To run regression sanity for IP uvmt_cvmcu_chip using the Metrics DSim Cloud simulator:

mio regr uvmt_cvmcu_chip sanity -a mdc

Reports

IP	Sanity	Nightly	Weekly
uvmt_cvmcu_chip	Coming Soon	Coming Soon	Coming Soon
uvmt_apb_timer_ss	Tests	Tests	Tests
uvmt_apb_adv_timer_ss	Tests	Tests	Tests