Comments (3)
Sorry about the late reply. I just noticed that I didn't attach the probing code for local and constant memories and #5 should have brought them back.
And for your confusion interpreting the ArchProbe results - instead of answering the entire list of entangled questions I'd like to give you some general guidelines.
For the terminologies you might have been confused of:
- SmCount = Stream Multiprocessor (NVIDIA) Count = Execution Engine (Arm) Count = Shader Core (Qualcomm) Count = Number of SIMT units where several threads are executed together, i.e., number of bunches of ALUs.
- AluCount = Max Warp Size (NVIDIA) = Maximal number of threads that can be executed in an SM.
- RegCount = Number of registers. Also in our work we assumed that a single regsiter can hold a 32-bit floating point number for simplicity. Because people barely use double-precision computations on mobile devices; also to keep the probing code simple.
For cache sizes and memory bandwidths, you'd like to lookup records in {Image|Buffer}Bandwidth
and {Image|Buffer}CacheHierarchyPChase
. You should be aware that you CANNOT rely solely on the JSON report for cache level bandwidths. The algorithm might fail to identify large cache boundaries because of the noisy timing. The JSON report is merely an auto-genrerated brief of its discovery digested by, in out case, TVM. Unlike the fixed number of registers and memory size, aspects like memory bandwidths varies with respect to the range of access, and ArchProbe does utilize such properties to detect the cache sizes. So you should plot the results in the .csv
files to visualize how the bandwidth changes while the size of memory accessed increases. And the techniques to interpret the plots have already been illustrated in detail in our paper.
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I'm closing this issue but please feel free to reopen it if you have further concerns interpreting ArchProbe outputs.
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Thanks for your detail explanation, I will try to digest it.
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Related Issues (9)
- Get stuck when run ./ArchProbe on Adreno 640 on Meizu 16s HOT 2
- ImageCachelineSize causes memory object allocation failure on Mali-G78 HOT 1
- Global Memory to GPU Bandwidth HOT 2
- Does this contains the code to reproduce or generate the figures or data of the document? HOT 2
- How to calculate ALUs? HOT 4
- Continuous discussion about calculating the number of ALUs HOT 6
- question about "number of registers" HOT 4
- Is rooting required? HOT 4
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