AES加密解密算法的Verilog实现
AES加密解密算法的Verilog实现
本项目基于 Rudolf Usselmann 的实现代码，对其中的解密部分存在的错误进行了修正；并添加了简单的测试代码。
对于原作者的原始实现，已保存在git的commit记录之中。并且在每个文件头注释中，都保留了原作者信息。
Author: Rudolf Usselmann
Email: [email protected]
Site: www.asics.ws
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