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zybo implementation for xapp1078 which is an AMP example for zynq. CPU 0 runs linux and CPU1 runs bare-metal

License: GNU General Public License v2.0

C 15.05% C++ 1.52% Batchfile 0.01% Verilog 6.87% VHDL 55.36% Tcl 0.74% CartoCSS 0.01% HTML 19.22% CSS 0.03% Makefile 0.12% Assembly 0.74% JavaScript 0.04% Shell 0.02% TeX 0.01% Scala 0.17% SystemVerilog 0.03% Coq 0.10%

xapp1078_2014.4_zybo's Introduction

Readme

This project is to describe how to run xapp1078_2014.4 on a zybo board. The major difference between zybo and zc702 is:

DDR memory on zybo is 512MB while zc702 has 1GB
There are certain ii2 devices on zc702 that zybo doesn't have.
Ethernet PHY controller on zybo is different from that is used by zc702.

Based on that, changes are required on:

Set up a new vivado project and import the design for zc702 and generate new hdf and bit file for zybo board.
change boot args to limit linux on CPU0 only to use 384MB of DDR memory.
update system-top.dts for device on zybo.
Board support package (bsp) for CPU1 has to be changed to limit the usage of DDR memory to lower 128MB (0x18000000 to 0x1fffffff).

How to use this package

Basically, this package has the same layout as that given by xilinx. The difference is that:

work directory has been created for zybo. At this moment I don't know how to use tcl to create and set up a project successfully. I tried, but it doesn't work. If anyone knows how to do it, please let me know.
design/generated_files/ contains BOOT.BIN and image.ub for zybo board.
docs/Vivado instructions.txt has been modified to show the changes for zybo board.

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