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worth-reading-the-android-technical-articles

值得阅读的android技术文章

x-rust-freertos

FreeRTOS rewritten in Rust.

xapp1078_2014.4_zybo

zybo implementation for xapp1078 which is an AMP example for zynq. CPU 0 runs linux and CPU1 runs bare-metal

zeal

Offline documentation browser inspired by Dash

zedboard

zedboard-axi-dma

Demonstration of the AXI DMA engine on the ZedBoard

zedboard_intergrating_hls_ip_and_ddr

This is a project integrating HLS IP and CortexA9 on Zynq. This project implements DDR3 random access with HLS. The Cortex A9 will print the result via UART.

zephyr-inside

揭秘 Zephyr OS

zephyr-rak5010

A BLE to GPRS/NB-IoT industrial gateway

zrobot_v1

The robot base on ZedBoard

zynq-amp-xlnx

Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors

zynq-cookbook

This is a wiki and code sharing for ZYNQ

zynq-custom-board-bring-up-guide

This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project that can help to investigate a bring-up problem.

zynq-microzed-vivado-workshop

Zynq Workshop for Beginners

zynq-mmu-caches-control

A guide to controlling the Zynq Cortex A9 MMU / Caches, and a guide showing how to create custom software libraries in Xilinx SDK.

zynq-soc-training

Zynq SoC Training By EmbeddedCentric.com

zynq-zedboard-vivado-workshop

Zynq Workshop for Beginners

zynq_custom_core_templates

Sample HDL Code that Interfaces to the Zynq AXI Bus

zynq_examples

zynq_hls_ddr_dataflow_kernel_2mm

This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation

zynq_ps_only_standalone_apps

zynqbook

zynqbtc

A Bitcoin miner for the Zynq chip utilizing the Zedboard.

zynqdocumentation

zynqgnuradio

FPGA accelerator on GNU Radio and Zynq SoC

zynqrelated