For more information and updates: http://alexforencich.com/wiki/en/verilog/pcie/start
GitHub repository: https://github.com/alexforencich/verilog-pcie
Collection of PCI express related components. Includes PCIe to AXI and AXI lite bridges, a simple PCIe AXI DMA engine, and a flexible, high-performance DMA subsystem. Currently supports operation with the Xilinx UltraScale and UltraScale+ PCIe hard IP cores with interfaces between 64 and 512 bits. Includes full cocotb testbenches that utilize cocotbext-pcie and cocotbext-axi.
The pcie_us_axi_master
and pcie_us_axil_master
modules provide a bridge
between PCIe and AXI. These can be used to implement PCIe BARs. The
pcie_us_axil_master module is a very simple module for providing register
access, supporting only 32 bit operations. The pcie_us_axi_master
module is
more complex, converting PCIe operations to AXI bursts. It can be used to
terminate device-to-device DMA operations with reasonable performance. The
pcie_us_axis_cq_demux
module can be used to demultiplex PCIe operations based
on the target BAR.
The pcie_us_axi_dma
module provides a DMA engine with an internal AXI
interface. The AXI interface width must match the PCIe interface width. The
module directly translates AXI operations into PCIe operations. As a result,
it is relatively simple, but the performance is limited due to the constraints
of the AXI interface. Backpressure on the AXI interface is also passed
through to the PCIe interface.
The pcie_axi_dma_desc_mux
module can be used to share the AXI DMA module
between multiple request sources.
The split DMA interface/DMA client modules support highly flexible, highly performant DMA operations. The DMA interface and DMA client modules are connected by dual port RAMs with a high performance segmented memory interface. The segmented memory interface is a better 'impedance match' to the PCIe hard core interface - data realignment can be done in the same clock cycle; no bursts, address decoding, arbitration, or reordering simplifies implementation and provides much higher performance than AXI. The architecture is also quite flexible as it decouples the DMA interface from the clients with dual port RAMs, enabling mixing different client interface types and widths and even supporting clients running in different clock domains without datapath FIFOs.
The dma_if_pcie_us
module connects the Xilinx UltraScale PCIe interface to
the segmented memory interface. Currently, it does not support TLP straddling,
but it should be possible to support this with the segmented interface.
The dma_psdpram
module is a dual clock, parallel simple dual port RAM module
with a segmented interface. The depth is independently adjustable from the
address width, simplifying use of the segmented interface. The module also contains a parametrizable output pipeline register to improve timing.
The dma_if_mux
module enables sharing the DMA interface across several DMA
clients. This module handles the tags and select lines appropriately on both
the descriptor and segmented memory interface for plug-and-play operation
without address assignment - routing is completely determined by component
connections. The module also contains a FIFO to maintain read data ordering
across multiple clients. Make sure to equalize pipeline delay across all
paths for maximum performance.
DMA client modules connect the segmented memory interface to different internal interfaces.
The dma_client_axis_source
and dma_client_axis_sink
modules provide support
for streaming DMA over AXI stream. The AXI stream width can be any power of
two fraction of the segmented memory interface width.
General-purpose parametrizable arbiter. Supports priority and round-robin arbitration. Supports blocking until request release or acknowledge.
Frame-aware AXI stream arbitrated multiplexer with parametrizable data width and port count. Supports priority and round-robin arbitration.
AXI stream sink DMA client module. Uses a segmented memory interface.
AXI stream source DMA client module. Uses a segmented memory interface.
DMA interface mux module. Enables sharing a DMA interface module between
multiple DMA client modules. Wrapper for dma_if_mux_rd
and dma_if_mux_wr
.
DMA interface mux module. Enables sharing a DMA interface module between multiple DMA client modules. Muxes descriptors and demuxes memory writes.
DMA interface mux module. Enables sharing a DMA interface module between multiple DMA client modules. Muxes descriptors, demuxes memory read commands, and muxes read data.
PCIe DMA interface module for Xilinx UltraScale series FPGAs. Supports 64,
128, 256, and 512 bit datapaths. Uses a double width segmented memory
interface. Wrapper for dma_if_pcie_us_rd
and dma_if_pcie_us_wr
.
PCIe DMA interface module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit datapaths. Uses a double width segmented memory interface.
PCIe DMA interface module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit datapaths. Uses a double width segmented memory interface.
DMA RAM module. Segmented simple dual port RAM to connect a DMA interface module to a DMA client.
Descriptor multiplexer/demultiplexer for PCIe AXI DMA module. Enables sharing the PCIe AXI DMA module between multiple request sources, interleaving requests and distributing responses.
PCIe AXI DMA module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256,
and 512 bit datapaths. Parametrizable AXI burst length. Wrapper for
pcie_us_axi_dma_rd
and pcie_us_axi_dma_wr
.
PCIe AXI DMA module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit datapaths. Parametrizable AXI burst length.
PCIe AXI DMA module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit datapaths. Parametrizable AXI burst length.
PCIe AXI master module for Xilinx UltraScale series FPGAs. Supports 64, 128,
256, and 512 bit datapaths. Parametrizable AXI burst length. Wrapper for
pcie_us_axi_master_rd
and pcie_us_axi_master_wr
.
PCIe AXI master module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit datapaths. Parametrizable AXI burst length.
PCIe AXI master module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit datapaths. Parametrizable AXI burst length.
PCIe AXI lite master module for Xilinx UltraScale series FPGAs. Supports 64, 128, 256, and 512 bit PCIe interfaces.
Demux module for Xilinx UltraScale CQ interface. Can be used to route incoming requests based on function, BAR, and other fields. Supports 64, 128, 256, and 512 bit datapaths.
Demux module for Xilinx UltraScale RC interface. Can be used to route incoming completions based on the requester ID (function). Supports 64, 128, 256, and 512 bit datapaths.
Configuration shim for Xilinx UltraScale series FPGAs.
MSI shim for Xilinx UltraScale series FPGAs.
Parametrizable priority encoder.
Parametrizable pulse merge module. Combines several single-cycle pulse status signals together.
arbiter.v : Parametrizable arbiter
axis_arb_mux.v : Parametrizable AXI stream mux
dma_client_axis_sink.v : AXI stream sink DMA client
dma_client_axis_source.v : AXI stream source DMA client
dma_if_mux.v : DMA interface mux
dma_if_mux_rd.v : DMA interface mux (read)
dma_if_mux_wr.v : DMA interface mux (write)
dma_if_pcie_us.v ; DMA interface for Xilinx UltraScale PCIe
dma_if_pcie_us_rd.v ; DMA interface for Xilinx UltraScale PCIe (read)
dma_if_pcie_us_wr.v ; DMA interface for Xilinx UltraScale PCIe (write)
dma_psdpram.v : DMA RAM (segmented simple dual port RAM)
pcie_axi_dma_desc_mux.v : Descriptor mux for DMA engine
pcie_us_axi_dma.v : PCIe AXI DMA module (Xilinx UltraScale)
pcie_us_axi_dma_rd.v : PCIe AXI DMA read module (Xilinx UltraScale)
pcie_us_axi_dma_wr.v : PCIe AXI DMA write module (Xilinx UltraScale)
pcie_us_axi_master.v : PCIe AXI Master module (Xilinx UltraScale)
pcie_us_axi_master_rd.v : PCIe AXI Master read module (Xilinx UltraScale)
pcie_us_axi_master_wr.v : PCIe AXI Master write module (Xilinx UltraScale)
pcie_us_axil_master.v : PCIe AXI Lite Master module (Xilinx UltraScale)
pcie_us_axis_cq_demux.v : Parametrizable AXI stream CQ demux
pcie_us_axis_rc_demux.v : Parametrizable AXI stream RC demux
pcie_us_cfg.v : Configuration shim for Xilinx UltraScale devices
pcie_us_msi.v : MSI shim for Xilinx UltraScale devices
priority_encoder.v : Parametrizable priority encoder
pulse_merge : Parametrizable pulse merge module
Running the included testbenches requires cocotb, cocotbext-axi, cocotbext-pcie, and Icarus Verilog. The testbenches can be run with pytest directly (requires cocotb-test), pytest via tox, or via cocotb makefiles.