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Hello, I'm MaharshiπŸ‘‹

I'm a senior software engineer with a passion for crafting scalable distributed systems and leveraging the power of JavaScript and TypeScript to build robust applications. My expertise lies in designing and implementing solutions that thrive in distributed environments, with a particular focus on Node.js and Nest.js frameworks. Holding an AWS Solutions Architect certification, I enjoy architecting cloud-native applications that seamlessly integrate with AWS services

πŸ”§ Technologies & Expertise

  • Languages: JavaScript, TypeScript
  • Frameworks & Technologies: Node.js, Nest.js, Express.js, AWS (Lambda, DynamoDB, S3, etc.)
  • Distributed Systems: Designing, implementing, and scaling distributed systems for resilience, high availability and fault tolerance

πŸŽ“ AWS Certification

  • AWS Certified Solutions Architect: [Associate] - Leveraging AWS services to architect scalable and resilient solutions.

πŸ’Ό Current Focus

  • Currently diving deeper into Typescript, Nest.js as well as exploring new possibilities in distributed computing and cloud architecture.

Feel free to connect with me on https://www.linkedin.com/in/maharshi-shah1996ms/ for further discussions and collaborations!

Maharshi Shah's Projects

array-explorer icon array-explorer

⚑️ A resource to help figure out what JavaScript array method would be best to use at any given time

clothing-webstore icon clothing-webstore

React based clothing webstore with Hooks, Redux, GraphQL, Firebase, Styled Components

computer-system-design icon computer-system-design

Finite State Machine on Anvyl Spartan-6 FPGA: The purpose of this project is to learn and practice synthesizable FSM construction to be tested on a FPGA board in Verilog. Design an FSM for use as a controller for a vending machine. The system has five (5) inputs: quarter, nickel, dime, soda, and diet. Further details in the project description.

digital-circuit-synthesis icon digital-circuit-synthesis

Provided with code of the clique partitioning algorithm implementation in C, develop several modules which can call the clique partitioning code to build the datapath synthesis tool. Read project description for further details.

fpga-design_1 icon fpga-design_1

VHDL project to build a count-down timer with preset time using the seven-segment display. Basys-3 FPGA board has been used to test and verify correctness. Further details in project description.

fpga-design_2 icon fpga-design_2

VHDL project for designing a simple digital lock to provide an approach for identity authentication. This lock operates in three modes: programming, normal and locked. Basys-3 FPGA board used to test and verify correctness of the FSM built for the digital lock. Further details in the project description.

fpga_matop icon fpga_matop

Implementing and testing matrix multiplication/addition algorithms on FPGA boards. – Input matrices are sent to FPGA from host terminal – Operations of FPGA are sent from host terminal β€’ The above two need UART receiver – After the algorithm is finished, the results are displayed in a terminal on the host system through a UART transmitter

javascript-algorithms icon javascript-algorithms

πŸ“ Algorithms and data structures implemented in JavaScript with explanations and links to further readings

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