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Project to illustrate issue with writing to memory on LiteX
The VexRiscv has both instruction and data cache.
Try adding these two lines to flush the cache before you have the CPU read from this shared memory.
greg@xps:~/projects/loxodes/dma_burst/firmware (master) $ git diff main.c
diff --git a/firmware/main.c b/firmware/main.c
index 4a2972c..6e42635 100644
--- a/firmware/main.c
+++ b/firmware/main.c
@@ -101,6 +101,10 @@ static void wishbone_test(void)
;
}
+ /* Flush cache */
+ flush_cpu_icache();
+ flush_cpu_dcache();
+
printf("memory readback!\n");
for(uint16_t i=0; i<64; i++) {
printf("memory[%d]: %d\n", i, dram_array[i]);
I don't have a evn_ecp5, but I've tried this on the OrangeCrab and was replicating your experience, this seems to fix the issue.
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