loganleland / llvm

Mirror of official llvm git repository located at http://llvm.org/git/llvm. Updated every five minutes.

LLVM

This directory and its subdirectories contain source code for LLVM, a toolkit for the construction of highly optimized compilers, optimizers, and runtime environments. On top of LLVM 3.9, an experimental backend targeting ANSI C is being implemented for the PIC16F877 in lib/Target/PIC16.

LLVM is open source software. You may freely distribute it under the terms of the license agreement found in LICENSE.txt.

Please see the documentation provided in docs/ for further assistance with LLVM, and in particular docs/GettingStarted.rst for getting started with LLVM and docs/README.txt for an overview of LLVM's documentation setup.

If you are writing a package for LLVM, see docs/Packaging.rst for our suggestions.

PIC16F877

A microcontroller created by MicroChip, more details can be found here: http://www.microchip.com/wwwproducts/en/PIC16F877A

Quick Start

This repo can be built from source. To do this, follow the offical LLVM guide to building: http://llvm.org/docs/CMake.html

Alternatively this project's binaries can be downloaded: This executable was built using Debian Jessie, although it should work for any x86 linux operating system.

wget https://github.com/loganleland/llvm/releases/download/rc1/pic16rc1.tar.gz
tar -zxvf pic16rc1.tar.gz
PATH=$PATH:$PWD/PIC16rc1

Usage

If you downloaded the binary:

compilePIC16 source.c

If you built from source:

postLLC can be found at llvm/lib/Target/PIC16/postLLC.sh

clang -S -emit-llvm -target pic16 source.c
llc -mcpu=generic -march=pic16 source.ll
postLLC.sh source.s

Survey

While using this compiler it would be greatly beneficial to the developers of this backend if you fill out the following survey: https://goo.gl/forms/AYxzRiEtKxIy9aBy2

Limitations

This backend is a preliminary prototype undergoing active development. Pull requests are very welcome.

Currently Supported:

• Functions
• Variable scoping
• Control Structures
• Variable assignment
• Integer addition/subtraction
• Bitwise operations: &,|,^
• integer comparisons: &&, ||, ==, !=

Compiler Overview

Languages

• ANSI C: Everyday C
• LLVM IR: LLVM's intermediate representation
• PIC16 ISA: PIC16F877's ISA

Compiler Phases

ANSI C

• ANSI C to LLVM IR clang

LLVM IR

• LLVM IR to Pre-PIC16 ISA llc

Pre-PIC16 ISA

• Pre-PIC16 ISA to PIC16 ISA postLLC: Transforms the llc output assembly into PIC16 ISA (will be removed once assembler is implemented)

PIC16 ISA

• PIC16 ISA to Byte-code mpasm

Future Work

• Implement assembler
• Implement multiplication and division
• Implement more integer comparisons
• Refactor
• Create API for timing, I/O ports, etc
• Currently our implementation is confined to one out of the four available banks of general purpose registers. Using more of these banks would allow for more variables
• Implement vector support

llvm's Issues

Assertion Failed in Clang

This assertion fails when compiling C -> ASM via Clang. Compiling C -> IR -> ASM via Clang + LLD does not produce this error. I have not applied the ASM correction script.

This error only happened when compiling addrr.c and andrr.c, so I suppose it has to do with register-register transfers specifically.

Attaching log
addrr-a8a8be.txt

ADDLW/SUBLW has no DAG pattern, inherits from wrong class

The code for ADDLW and SUBLW looks as follows currently:

def ADDLW  : I8rr<0x0,
                   (outs), (ins GR8:$src),
                   "addlw\t{$src}",
                   []>;

def SUBLW  : I8rr<0x0,
                   (outs), (ins GR8:$src),
                   "sublw\t{$src}",
                   []>;

The problems here are:

• No DAG pattern, so there is no matching. These instructions must be lowered manually.
• The W Register isn't implemented, so there are no DAG node... anchors? edges? I'm not too sure how LLVM refers to it. Regardless, these nodes have 1 input and 0 outputs.
• They inherit from I8rr instead of I8ri. Attempting to change it myself results in compilation errors, so @loganleland will need to fix it, since he knows what he changed to put it in.

I'll also point out that "SUBWF" and "SUBLW" are "Subtract W from the incoming data," so it looks like W = L - W and d = F - W. W should be $src2

Warning: Unused variable

When compiling currently we have an unused variable. It seems prologue and epilogue don't use Instruction Info. NOPE not that function.

/home/developer/Projects/llvm-nope/llvm/lib/Target/PIC16/PIC16FrameLowering.cpp:214:26: warning: unused variable 'TII' [-Wunused-variable]
  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
                         ^
/home/developer/Projects/llvm-nope/llvm/lib/Target/PIC16/PIC16FrameLowering.cpp:233:26: warning: unused variable 'TII' [-Wunused-variable]
  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();

Stack Pointer Calculation Tightness

Currently each stack frame has a size of at least 4 (parent FP, current FP, 2 regs for data) by default. There are two ways to tighten the size of each stack frame:

(1 Also there doesn't need to be a register for current FP. The FP reg (0x31) can point to where the parent FP is stored on each stack frame and use that to calculate the offsets for memory.

(2 Make the default SP calculation not include two reg's for local data by default