Microcoded instruction set processor in VHDL
You will need to have installed:
- Vivado Design Suite
- Python (optional)
- Clone the repo
git clone https://github.com/lexesjan/vhdl-processor.git
- Open Vivado and click
Open Project
- Open the
vhdl-processor.xpr
file - Modify the program in the memory (optional)
- Go to the
assembler
directory
cd assembler
- Edit the
in.txt
file - Run the following command
python assemble.py < in.txt | python formatter.py
- Copy the output into the
memory_512x16bits.vhd
file
- Go to the
- Run the simulation
- Click
Run Simulation
then - Click
Run Behavioral Simulation
- Click
Discussion of the simulation results
Mnemonic | Instruction | Syntax | Action |
---|---|---|---|
add | Add | adi Rd, Rn, Rm | Rd := Rn + Rm |
adi | Add with immediate | adi Rd, Rn, #Const | Rd := Rn + Const |
b | Branch | b Offset | PC := PC + Offset |
bne | Branch not equal | bne Offset, Rn | PC := PC + Offset if Z = '0' |
inc | Increment | inc Rd, Rn | Rd := Rd + 1 |
ld | Load | ld Rd, [Rn] | Rd := Mem.halfword[Rn] |
not | Bitwise not | not Rd, Rn | Rd := ~Rn |
sr | Shift right | sr Rd, Rn | Rd := Rn >> 1 |
st | Store | st [Rn], Rm | Mem.halfword[Rn] := Rm |