lavine2011 Goto Github PK

rsa-verilog

rvcc

sap-voicebox

Speech Processing Toolbox for MATLAB

saxonsoc

SoC based on VexRiscv and ICE40 UP5K

scratch-gui

Graphical User Interface for creating and running Scratch 3.0 projects.

scratch-www

Standalone web client for Scratch

sd-card-controller

WISHBONE SD Card Controller IP Core

sdr5

Design files for sdr5 prototype (Zynq + AD9363)

sensorfusion-ukf

激光雷达和毫米波雷达数据融合基于无迹卡尔曼滤波算法c++工程项目

serv

SERV - The SErial RISC-V CPU

skywater-130nm

ASIC Design kit for Skywater 130 for use with mflowgen

sm3-verilog

sm4-verilog

snowboy

DNN based hotword and wake word detection toolkit

speechrecognition

A local auto speech recognition project based on Kaldi and ALSA.

spinalhdl_cnn_accelerator

CNN accelerator implemented with Spinal HDL

stmbl

AC Servo Driver for STM32F4

tengine

Tengine is a lite, high performance, modular inference engine for embedded device

thinkdsp

Think DSP: Digital Signal Processing in Python, by Allen B. Downey.

tinymaix

TinyMaix is a tiny inference library for microcontrollers (TinyML).

tinyriscv

A very simple and easy to understand RISC-V core.

torchlm

💎A pipeline for face landmarks detection, can install via pip.

trajectorycontrol

用于无人船轨迹跟踪控制

tree-core-ide

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

uhd

The USRP™ Hardware Driver Repository

ultra-light-fast-generic-face-detector-1mb

💎1MB lightweight face detection model (1MB轻量级人脸检测模型)

uvm_candy_lover

:candy:UVM candy lover testbench which uses YASA as simulation script

ventus-gpgpu

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

verilog-fixedpoint

A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

video_systems

Video compression systems