Bus-idle flag is cleared after the UART receive complete interrupt fires, that is after the first byte of the message is received. This is far too late. This flag should be cleared as soon as the first start bit (0) appears on the CCD-bus.
Possible solution 1:
The RX-pin can't be used as an external interrupt source because it is controlled by the hardware UART. So first disable UART receiver and use RX-pin as an external interrupt source. Once the falling edge is sensed it's probably not too late to re-enable the UART receiver, clear the bus-idle flag and still be able to sense the start bit.
Possible solution 2:
Connect RX-pin to another external interrupt capable pin and let it handle clearing the bus-idle flag while UART receiver is always enabled.
Something is wrong with the timer setup or how the timer is used, because every byte on the CCD-bus is interpreted as a new message. The timer thinks that more than 10-bit time (1280 microseconds) elapses between the received bytes.
Temporary solution is to increase bus-idle time to 14-bit in the begin() function. In this case every message appears to be good.
This issue doesn't affect the CDP68HC68S1 chip because bus-idle condition is recognized by the chip itself and signaled to the microcontroller via an interrupt.
Right now the first two states are established by an interrupt / timer task.
The third state is a simple 256 us delay right before writing data to the CCD-bus.
The fourth arbitration state is determined during the transmission of the first ID byte.
It would be much better if the same idle-timer would determine the first 3 states in the background.
The third state is especially sensitive to blocking delays.
An enumerated variable could store all 4 states in one place.