kramble / fpga-litecoin-miner Goto Github PK

Getting the following with the latest code, set for two cores
There seems to be one more valid hash for 71 !!, everything else is no error

Tested 70 passed 70 fail 0 unmatched 0
Test 000007ff0043e4ce9a6c491b3119fb516030a368196617e5c5c901d562f24416dd1dda66db011278b8c2b2cb93383c7de354106474bee7afe991e590271b6e679e74eb1716340b5a0957589f04a1cf3601000000
Share found on Sat Nov 30 15:00:50 2013 nonce 0043e500
... CORRECT
Tested 71 passed 71 fail 0 unmatched 0
Test 000007ff00227f0b9a6c491bad19fb51e6597f5ca35e7f9f83b9aa228e457c5d7b4693c473028b34be5db64fe8178b93330429ae8107d2beddb7ff90a46f7fe0b1321e5ad4c3dba805341698445f6f7102000000
Share found on Sat Nov 30 15:00:50 2013 nonce 10227f2b
... ERROR expected nonce 0x227f3d
Share found on Sat Nov 30 15:00:50 2013 nonce 00227f3d
... CORRECT

Hi,
Is this possible with stratum support? Thank you!

Dear Kramble:
I was trying to run your code on my DE2-115 evaluation board. I managed to optimize it and I've got an output of 6.20 kHash/sec using 1024kBit that technically would allow me to instantiate 3 harshcores, so I could reach 18.6 kHash/sec without external memory. I also succeed to make it work the 512kBit version, but with your forecasted penalty of getting only 80% of the performance, so I've got 5.02 kHash/sec for a single core and I potentially could instantiate 7 harshcores in it, bringing my output to 35.14 kHash/sec, with a power consumption of around 7.5W. But when I tried your approach to instantiate more harshcore (I am trying just 2 at this point, as prove of concept) Quartus shows me that the compilation went through and allocated memory and logical elements doubled and the hierarchy shows all elements there, but when I run your miner script it still gives me 6.20 kHash/sec, making me believe that either the multicore instantiation is not kicking in or that your mine tcl is not capturing the extra jobs. I am not proficient with tcl so I was wondering if you could help me here. Also, although I am proficient with FPGA's, this is the first time I am using the virtual wires in a project. I tried different approaches for the queue you suggested, using a flag to alternate the golden_nonce_out that is produced. I run out of ideas. Is this the best way to contact you?
Rgds,
Hagar, the Horrible

Hi,
It seems that ltcminer.py is only showing half the nonces in the count. (or litecoin is double crediting.)

The below run..

./ltcminer.py
Miner started on Wed Aug 14 15:14:30 2013
Sending data to FPGA
Payload 00007fff6c6f6f700bf84c1b582e0b5272ae7ba598a8d632ad31b86e7a92756a2e169cee718b7d23efd35579644b2157d0ede2df8d6ceb2aee663f19c0685f21abab29d9727500b3c9231d34860195d002000000
Share found on Wed Aug 14 15:14:38 2013 nonce 0c6faa2f
Sending data to FPGA
Payload 00007fff6c6f6f700bf84c1b5e2e0b528b4a95a1f0bc3a01f2eb237b6e0b16c83a247a0d455d8424ca98c2873e4bf009d0ede2df8d6ceb2aee663f19c0685f21abab29d9727500b3c9231d34860195d002000000
Upstream result: True
[1 accepted, 0 failed, 266.25 +/- 266.25 khash/s]
^CTerminated

According to this we have 1 share that was accepted....

According to:
https://www.litecoinpool.org/account

we have :
Shares Stale shares Invalid shares
2 0 (0.00%) 0 (0.00%)

I can guarantee the count is correct at litecoin.org because it was a brand new miner account i created to test it....

but also.. if I leave it running for a while , the account on litecoin is always double what the python shows..

Hey, does anybody know of a way I can get this to compile to a Cyclone II EP2C35F672C6N? I have been trying for a while, now, and when I try to compile after opening the .qpf in Quartus and changing the device to mine, I get this error:

Error (272006): MGL_INTERNAL_ERROR: Port object altpll|clk of width 5 is being assigned the port altpll|stratixii_pll inst pll1|clk of width 3 which is illegal, as port widths dont match nor are multiples. CAUSE : The port widths are mismatched in the mentioned assignment. The port widths of the connected ports should match or the LHS port width should be a multiple of the RHS port width. ACTION : Check the port widths of the connected ports. Logical operation results in a port width equal to the larger of the two ports and concatenation results in a port width equal to the sum of the individual port widths. Double check for such cases.

(yeah...it's long)

There's also these two warnings:

Warning (10230): Verilog HDL assignment warning at ltcminer.v(83): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at ltcminer.v(124): truncated value with size 32 to match size of target (2)

I don't have much experience compiling for other boards, admittedly. If nobody knows the specific answer, I would super super appreciate either some help, some tips, or a kick in the right direction.

I'm doing this in Linux, by the way.

THANK YOU.

Are the same steps taken to get up and running with this project the same as the bitcoin version? What is the best hardware in terms of cost per hashrate? Is there any docs on how to get it up and going?

Great project, thanks!

I am having a little trouble comparing these two pieces of hardware.
what sort of output can I expect after reaching safe OC settings? and would it be better to go the route of several DE0-nanos as apposed to 1 DE2-115?

Also, as this is compatible with litecoin, would it be easily configurable to mine other alt coins?

My board is de2-115, and I transmitted the generated sof to my board. However, the ltminer run good, but the the hashrate is only about 1.44kH/s, which was far from your previous guess (8kH/s). Even worse part was that the pool didn't display my worker's hashrate. This is so wearied. Was my hashrate invalid? why not rejected?

Please help me through this problem, and thanks in advance.

When I set LOCAL_MINERS=2, should I expect to see an increased hash rate? I can see that the resource utilization has doubled, but the speed remains 2.33kH/s:

new target 00000492 diff 56
06f0aafb416d8e9e0aa8595a788ff8e91384ebe2135839f57367383302000000
c9126b44155767a6345f2a8e2dd9c8aef91396a71c77a80fa8f3597b2026921c
00000000000000000000000080000000000000005bd7101b525ed3526fd8e104
target 00000492
[01/12/2014 19:33:08] 2.33 kH/s (~0.00 kH/s) [Rej: 0/0 (0.00%)] n=0006f64e
[01/12/2014 19:33:10] 2.33 kH/s (~0.00 kH/s) [Rej: 0/0 (0.00%)] n=00070879
[01/12/2014 19:33:12] 2.33 kH/s (~0.00 kH/s) [Rej: 0/0 (0.00%)] n=00071aa3
[01/12/2014 19:33:14] 2.33 kH/s (~0.00 kH/s) [Rej: 0/0 (0.00%)] n=00072cce
[01/12/2014 19:33:16] 2.33 kH/s (~0.00 kH/s) [Rej: 0/0 (0.00%)] n=00073ef7
[01/12/2014 19:33:18] 2.33 kH/s (~0.00 kH/s) [Rej: 0/0 (0.00%)] n=00075122

is there something in the scripts side to enable multiple cores?

dear sir:

 thanks for your work. 

I want to use the fpga-litecoin-miner on Nexys4 Artix-7 FPGA Board Xilinx FPGA。

thanks

maybe we could get this working on the below fpga with built in memory controller.
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=816&PartNo=2

FPGA Device

Cyclone V SX SoC—5CSXFC6D6F31C8NES
110K LEs, 41509 ALMs
5140 M10K memory blocks
6 FPGA PLLs and 3 HPS PLLs
2 Hard Memory Controllers
3.125G Transceivers
ARM®-based hard processor system (HPS)

800 MHz, A Dual-Core ARM Cortex™-A9 MPCore™ Processor
512 KB of shared L2 cache
64 KB of scratch RAM
Multiport SDRAM controller with support for DDR2, DDR3, LPDDR1, and LPDDR2
8-channel direct memory access (DMA) controller
Configuration and Debug

Quad Serial Configuration device – EPCQ256 for FPGA
On-Board USB Blaster II (micro USB type B connector)
Memory Devices

1GB (2x256MBx16) DDR3 SDRAM on FPGA
1GB (2x256MBx16) DDR3 SDRAM on HPS
128MB QSPI Flash on HPS
Micro SD Card Socket on HPS
EPCQ256 Flash on FPGA
Communication

USB 2.0 OTG (ULPI interface with micro USB type AB connector)
USB to UART (micro USB type B connector)

10/100/1000 Ethernet

I set it up to test on my bemicro and the mine.bat runs fine, but theres an error "ERROR: Unable to getwork. Reason: key "result" not known in dictionary."

Would that be an error with the mining pools I'm member to, or did I miss a file or something?

I took all the files from "scripts" "source" and "bemicro" do I need a stratum proxy to mine?

program-fpga-board.bat

no files matched glob pattern "*.sof"
while executing
"glob *.sof"
invoked from within
"set sof_files [glob *.sof]"
(file "program-fpga-board.tcl" line 69)

Error (23031): Evaluation of Tcl script program-fpga-board.tcl unsuccessful
Error: Quartus Prime Signal Tap was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 424 megabytes
Error: Processing ended: Tue Oct 19 23:38:12 2021
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:00
Presione una tecla para continuar . . .

My config.tcl
set url "http://XX.XX.XX.XX:8332"
set userpass "myuser.myworker:mypass"

I downloaded mining_proxy.exe from https://github.com/slush0/stratum-mining-proxy. then run cmd.exe
mining_proxy -o litecoinpool.org -p 3333

I get this error when i run mine.bat

When i start the miner, i get this message.

ZTEX PT02-04-08-4: Found Ztex (fpga count = 4) , mark as 3

is a faulty fpga? or isd any problem on my side (human error)

Ok , ran the Lx150 code on a single device , but set it to one internal core.

The ' ./ltcminer.py' does not seem to return a valid hash every time when testing.
(but it IS correct when it does)
(ignore the kh/s, they are nonsense..... I wish they were not)

./ltcminer.py
Miner started on Sun Aug 11 07:19:17 2013
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Share found on Sun Aug 11 07:19:26 2013 nonce 0000318f
Share found on Sun Aug 11 07:19:26 2013 nonce 0000318f
Upstream result: False
[0 accepted, 1 failed, 199.73 +/- 199.73 khash/s]
Upstream result: False
[0 accepted, 2 failed, 398.73 +/- 281.95 khash/s]
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Share found on Sun Aug 11 07:20:38 2013 nonce 0000318f
Share found on Sun Aug 11 07:20:38 2013 nonce 0000318f
Upstream result: False
[0 accepted, 3 failed, 76.41 +/- 44.11 khash/s]
Upstream result: False
[0 accepted, 4 failed, 101.85 +/- 50.92 khash/s]
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Share found on Sun Aug 11 07:26:21 2013 nonce 0000318f
Upstream result: False
[0 accepted, 5 failed, 24.68 +/- 11.04 khash/s]
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Share found on Sun Aug 11 07:26:30 2013 nonce 0000318f
Share found on Sun Aug 11 07:26:30 2013 nonce 0000318f
Upstream result: False
[0 accepted, 6 failed, 28.94 +/- 11.81 khash/s]
Upstream result: False
[0 accepted, 7 failed, 33.76 +/- 12.76 khash/s]
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Share found on Sun Aug 11 07:26:40 2013 nonce 0000318f
Upstream result: False
[0 accepted, 8 failed, 37.75 +/- 13.35 khash/s]
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Share found on Sun Aug 11 07:29:36 2013 nonce 0000318f
Share found on Sun Aug 11 07:29:36 2013 nonce 0000318f
Upstream result: False
[0 accepted, 9 failed, 30.44 +/- 10.15 khash/s]
Upstream result: False
[0 accepted, 10 failed, 33.82 +/- 10.70 khash/s]
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Share found on Sun Aug 11 07:29:46 2013 nonce 0000318f
Share found on Sun Aug 11 07:29:46 2013 nonce 0000318f
Upstream result: False
[0 accepted, 11 failed, 36.62 +/- 11.04 khash/s]
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Upstream result: False
[0 accepted, 12 failed, 39.94 +/- 11.53 khash/s]
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Share found on Sun Aug 11 07:30:16 2013 nonce 0000318f
Share found on Sun Aug 11 07:30:16 2013 nonce 0000318f
Upstream result: False
[0 accepted, 13 failed, 41.29 +/- 11.45 khash/s]
Upstream result: False
[0 accepted, 14 failed, 44.46 +/- 11.88 khash/s]
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Share found on Sun Aug 11 07:31:07 2013 nonce 0000318f
Share found on Sun Aug 11 07:31:07 2013 nonce 0000318f
Upstream result: False
[0 accepted, 15 failed, 44.21 +/- 11.42 khash/s]
Sending data to FPGA
Payload 000007ff000000007e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000
Upstream result: False
[0 accepted, 16 failed, 47.16 +/- 11.79 khash/s]