Implementation of the background subtraction algorithm on an FPGA for real time object detection.
Method: Background Subtraction
Hardware: Altera DE2 Cyclone II (FPGA) CMOS TRDB-D5M (Camera)
Preview: https://www.youtube.com/watch?v=b_YE6aiNQmE
Project developed for the 2014/2015 edition of the Digital Systems Design course (Laboratório de Sistemas Digitais) by Bruna Nogueira and Ricardo Mendes