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Verilog to Routing -- Open Source CAD Flow for FPGA Research

Home Page: https://verilogtorouting.org

License: Other

Shell 0.15% CMake 0.18% Dockerfile 0.01% Makefile 0.12% C++ 14.50% C 61.40% Yacc 0.12% Lex 0.06% Verilog 20.25% Coq 0.01% Python 0.61% Perl 0.97% HTML 1.41% Objective-C 0.04% Batchfile 0.01% Lua 0.01% JavaScript 0.11% CSS 0.01% SourcePawn 0.01% Perl 6 0.07%

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