[华中科技大学] 数电实验，基于Logism
本实验首发于Gitee
华中科技大学数字电路实验 计算机专业 仅供参考，如有错误欢迎指正（直接写到issue里就行）
QQ : 462241980 欢迎来找我吹水
参考资料：GitHub - SSA2001/HUST_Digital_circuit: 华中科技大学数字电路实验
这个比较简单就不多说明了，自己搜资料就行
实验一加法器做的时候忘了封装了，记得封装
在写的时候没有看到12/24互转的要求，就在最外层封装里做的转换
具体实现方法是底层都用24小时实现，通过24转12来实现输出
更优的输出方法是封装在计数器内部，有兴趣可以实现一下（注意转换时要输出进位脉冲来反转AM/PM）
如果提示找不到加载库，选择目录下的“1 加法器”文件即可（调用了四位二进制并行加法器）
写的时候没有注意到闹钟功能需要共用显示屏，不过是选做功能我就没管了
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