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MIPS Single Cycle

A single-cycle, functional processor simulator according to the reduced MIPS R3000 ISA. This project is developed for 2014 Spring CS410001-Computer Architecture course offerd by Prof. Ren-Song Tsay @ National Tsing Hua University

Characteristic

  • To meet the needs in course, both the instruction memory and data memory are changed into little-endian format.
  • Register 0 is a hard-wired constant 0; any attempt to write to register 0 takes no effect.
  • Assume that both the instruction memory and data memory are of 1K bytes size.
  • An error handler is implemented to deal with erroneous instruction executions.
  • The execution of the single cycle processor simulator would terminate after executing the halt instruction.

Input format

For each test case, all registers, except PC and $sp, are initialized to 0’s; other initial conditions are specified in the following two files.
  • iimage.bin: The instruction image (little-endian format, encoded in binary). The first four bytes indicate the initial value of PC, i.e. the starting address to load the instruction image. The next four bytes specify the number of words to be loaded into instruction memory (I memory). The remaining are the program text to be loaded into I memory. All other addresses not covered by the image are assumed to have been initialized to 0’s.
  • dimage.bin: The data image (little-endian format, encoded in binary). The first four bytes show the initial value of $sp. The next four bytes indicate how many words to be loaded into data memory (D memory). The remaining are the data to be loaded into D memory, starting from address 0. The contents of all other addresses not covered by the image are assumed to have been initialized to 0’s.

Output format

For each test case, the simulator wiil generate the following two files respectively:
  • snapshot.rpt: contain all register values at each cycle.
  • error_dump.rpt: contain error messages.

Usage

Put the iimage.bin and dimage.bin in the working directory
  • make: compile single_cycle
  • make clean: clean cache and log files generated in compiling
  • execute single_cycle

Reference

Reduced MIPS R3000 ISA
  • R-format
  • R opcode(6) rs(5) rt(5) rd(5) shamt(5) funct(6)
    add 0x00 X 0x20
    sub 0x00 X 0x22
    and 0x00 X 0x24
    or 0x00 X 0x25
    xor 0x00 X 0x26
    nor 0x00 X 0x27
    nand 0x00 X 0x28
    slt 0x00 X 0x2A
    sll 0x00 X 0x00
    srl 0x00 X 0x02
    sra 0x00 X 0x03
    jr 0x00 X X X 0x08
  • I Type Instruction
  • I opcode(6) rs(5) rt(5) immediate(16)
    addi 0x08
    lw 0x23
    lh 0x21
    lhu 0x25
    lb 0x20
    lbu 0x24
    sw 0x2B
    sh 0x29
    sb 0x28
    lui 0x0F X
    andi 0x0C
    ori 0x0D
    nori 0x0E
    slti 0x0A
    beq 0x04
    bne 0x05
  • J Type Instruction
  • J opcode(6) address(26)
    jr 0x02
    jal 0x03
  • Special Type Instruction
  • S opcode(6) address(26)
    halt 0x3F X

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