AIM:
To implement the given logic function verify its operation in Quartus using Verilog programming.
F1= A’B’C’D’+AC’D’+B’CD’+A’BCD+BC’D
F2=xy’z+x’y’z+w’xy+wx’y+wxy
EQUIPMENT REQUIRED:
Hardware – PCs, Cyclone II , USB flasher
Software – Quartus prime
THEORY:
Logic gates are electronic circuits which perform logical functions on one or more inputs to produce one output.
AND gate :The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is used to show the AND operation i.e. A.B or can be written as AB Y= A.B
OR gate : The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A plus (+) is used to show the OR operation.Y= A+B
NOT gate : A NOT gate is a logic gate that inverts the digital input signal. For this reason, a NOT gate is sometimes is referred to as an inverter
PROCEDURE:
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Type the program in Quartus software.
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Compile and run the program.
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Generate the RTL schematic and save the logic diagram.
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Create nodes for inputs and outputs to generate the timing diagram.
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For different input combinations generate the timing diagram.
PROGRAM:
OUTPUT:
RTL
F1
F2
Truth table
Timing Diagram
RESULT:
Thus the given logic functions are implemented using and their operations are verified using Verilog programming.