jmahler / mips-cpu

MIPS CPU implemented in Verilog

NAME

mips-cpu - A MIPS CPU written in Verilog

DESCRIPTION

An implementation of a MIPS CPU written in Verilog. This project is in very early stages and currently only implements the most basic functionality of a MIPS CPU.

• 32-bit MIPS processor

• implemented in Verilog

• 5 stage pipeline

• static branch not taken branch predictor

• branch detection in decode (stage 2)

• supports stalls to avoid read after write (RAW) and other hazards

• can forward from memory (stage 4) and write back (stage 5) to avoid stalls

Much of the design was inspired by the book "Computer Organization and Design" by David A. Patterson and John L. Hennessy (4th ed. 2008).

This project also includes a full set of test benches. These are invaluable as a quick check to verify that new changes have not disrupted previously working functionality.

REQUIREMENTS

This project requires a Verilog simulator, such as Icarus, the Gcc compiler, and a Gcc MIPS cross compiler. To check if your system has the required programs installed run the check-install.sh script.

$ ./check-install.sh
Checking for required programs...
  mips-linux-gnu-objcopy
  mips-linux-gnu-as
  iverilog
Please install the missing programs and retry.

RUNNING TEST BENCHES

The tests are located in the verilog/test/ directory. Everything is built and run using the make command.

make

There are two parts to each test: the Verilog code, and the assembly code. The Verilog code uses a generic CPU test bench (cpu_tb.v) from which a specific test is built using a specific assembled .hex file. The .hex file is produced by assembling the .asm file using the Gcc MIPS cross compiler and converting it to ASCII hex suitable for use with Verilog. Then the Verilog code, using a simulator such as Icarus Verilog, can be run to execute the assembly instructions and produce a dump of its output (.out). Finally, the output file (.out) can be diffed against a known good output file (.check) to see if there are any differences.

For more information about these steps refer the Makefile in verilog/test/.

AUTHOR

Jeremiah Mahler [email protected]
http://github.com/jmahler

COPYRIGHT

Copyright © 2015, Jeremiah Mahler. All Rights Reserved.
This project is free software and released under the GNU General Public License.

mips-cpu's Issues

Register $0 should not be other value other than 0

$0 should be zero at all time

j-type instruciton seems not exactly right

for these instrucitons,

20080001
08000004
00000000
21080100
21080001

the first iterm is pc ,which seems is not exactly right,
the target address is 00000010 , there are two of them

What's going to happen when stall_s1_s2 from 1 to 0???

/* If an operation in stage 4 (MEM) loads from memory (e.g. lw)
	 * and the operation in stage 3 (EX) depends on this value,
	 * a stall must be performed.  The memory read cannot 
	 * be forwarded because memory access is too slow.  It can
	 * be forwarded from stage 5 (WB) after a stall.
	 *
	 *   lw $1, 16($10)  ; I-type, rt_s3 = $1, memread_s3 = 1
	 *   sw $1, 32($12)  ; I-type, rt_s2 = $1, memread_s2 = 0
	 *
	 *   lw $1, 16($3)  ; I-type, rt_s3 = $1, memread_s3 = 1
	 *   sw $2, 32($1)  ; I-type, rt_s2 = $2, rs_s2 = $1, memread_s2 = 0
	 *
	 *   lw  $1, 16($3)  ; I-type, rt_s3 = $1, memread_s3 = 1
	 *   add $2, $1, $1  ; R-type, rs_s2 = $1, rt_s2 = $1, memread_s2 = 0
	 */
	always @(*) begin
		if (memread_s3 == 1'b1 && ((rt == rt_s3) || (rs == rt_s3)) ) begin
			stall_s1_s2 <= 1'b1;  // perform a stall
		end else
			stall_s1_s2 <= 1'b0;  // no stall
	end

I cannot understand this, can someone help.

Hello,there is something puzzling me

Your code is pretty smart and concise.

Threre is something puzzling me in this file:

mips-cpu/test/cpu_tb.v

cpu#(.NMEM(NUM_IM_DATA), .IM_DATA(IM_DATA_FILE))
mips1(.clk(clk));

What are the first macro for? I can not figure it out, I can't find where IM_DATA_FILE is defined, either.

I would appreciate if I could get your help.