jiangnan7 / vicuna

RISC-V Zve32x Vector Coprocessor

Vicuna - a RISC-V Zve32x Vector Coprocessor

Vicuna is an open-source 32-bit integer vector coprocessor written in SystemVerilog that implements version 1.0 of the RISC-V "V" Vector extension specification . More precisely, Vicuna complies with the Zve32x extension, a variant of the V extension aimed at embedded processors that do not require 64-bit elements or floating-point support (see Sect. 18.2 of the specification for details). As such, Vicuna supports vector element widths of 8, 16, and 32 bits and implements all vector load and store, vector integer¹, vector fixed-point, vector integer reduction, vector mask, and vector permutation instructions.

Vicuna is a coprocessor and thus requires a main processor to function. It uses the OpenHW Group's CORE-V eXtension Interface as interface to the main core. Currently, a modified version of the Ibex core or the CV32E40X core serves as the main core. Support for further RISC-V CPUs is under development.

Vicuna is extensively configurable. For instance, the width of the vector registers, the number and layout of its execution pipelines and the width of its memory interface are configurable. The following figure gives a high-level overview of Vicuna.

Vicuna is under active development, and contributions are welcome!

Documentation

A high-level user guide for using Vicuna can be read online at ReadTheDocs.

Publication

If you use Vicuna in academic work, please cite our publication:

@InProceedings{platzer_et_al:LIPIcs.ECRTS.2021.1,
  author =  {Platzer, Michael and Puschner, Peter},
  title =   {{Vicuna: A Timing-Predictable RISC-V Vector Coprocessor for Scalable Parallel Computation}},
  booktitle =   {33rd Euromicro Conference on Real-Time Systems (ECRTS 2021)},
  pages =   {1:1--1:18},
  series =  {Leibniz International Proceedings in Informatics (LIPIcs)},
  ISBN =    {978-3-95977-192-4},
  ISSN =    {1868-8969},
  year =    {2021},
  volume =  {196},
  editor =  {Brandenburg, Bj\"{o}rn B.},
  publisher =   {Schloss Dagstuhl -- Leibniz-Zentrum f{\"u}r Informatik},
  address = {Dagstuhl, Germany},
  URL =     {https://drops.dagstuhl.de/opus/volltexte/2021/13932},
  URN =     {urn:nbn:de:0030-drops-139323},
  doi =     {10.4230/LIPIcs.ECRTS.2021.1},
  annote =  {Keywords: Real-time Systems, Vector Processors, RISC-V}
}

Getting Started

This repository uses submodules. After cloning the repository, run following command in the top directory to initialize the submodules:

git submodule update --init --recursive

Compiling programs

The sw/ subdirectory contains utilities for generating programs that can be executed on Vicuna.

Simulation

The sim/ subdirectory contains scripts for simulating Vicuna with either Verilator, xsim (the default simulator in Vivado), or Questasim. For Verilator, version 4.210 or newer is required.

Synthesis

The demo/ subdirectory contains a minimalist demo design for Xilinx FPGAs.

Configuration

Vicuna allows for extensive parametrization. In particular, the width of the vector registers, of the memory interface, and of the datapaths of the functional units can be configured independently.

License

Unless otherwise noted, everything in this repository is licensed under the Solderpad Hardware License v2.1, a permissive free software license that is based on the Apache-2.0 license.

The Ibex core (included in this repository as a submodule) is licensed under the Apache License, see the Ibex repository for details.

The CV32E40X core (included in this repository as a submodule) is licensed under the Solderpad Hardware License, see the CV32E40X repository for details.

Footnotes

1. Currently, the vector integer divide instructions (i.e., vdiv, vdivu, vrem, and vremu) are still missing. ↩