jakestevens / riscvbusiness Goto Github PK

The memory controller has fixed endianness. There should be a parameter that selects what endianness the output of the memory controller will be so RISCVBusiness can be compatible with any bus.

To enable ease of switching to 64/128 bit implementations, word length should be configurable. XLEN is the accepted RISCV terminology for this.
Not a pressing concern, as a 64 bit core is not on the current list of goals.

Cause:

The failure is due to the pipeline issuing an instruction fetch when an interrupt/exception is occuring and the PC is getting updated. The read request changes before completion, causing problems in the memory controller.

Solution:

The iREN signal should be masked when the PC is being updated by an exception/interrupt.

The following reorganizations need to occur to clean up the directory:

1. "rename ram_if" to "generic_bus_if"
2. Rename pipeline to nonpipeline bridge to "generic_ram_bridge" (or something similar)
3. Put all the RTL and TB into its own directory (includes, src, packages, fpga, tb)
4. Create subdir in src for bus bridges (generic_ram_bridge, ahb_bridge)
5. Create a new branch prediction file for the always not taken predictor and instantiate it in the branch predictor
6. Create subdirectory for branch predictors
7. Create subdirectory for performance/debug trackers (cpu_tracker, branch_tracker)

The idea is that anything that is swappable in our design (branch predictor, bus if) should have its own dir where each file in the dir follows a specific port mapping. We may choose to do this with icache and dcache too, if we want to allow different cache structures (coherent cache and non coherent caches).

It may be useful to have all our trackers in one dir so they aren't confused as source code for people initially looking through the repo. This allows us to also add more performance trackers without cluttering our base source directory.

Must fix tests cases: bgeu, bltu, sb, sh, sw, sll, sra, and srl

If the define file selects a component that does not exist, the user is not warned. Instead, the design will just silently fail all test cases. Some sort of check should be added to the configurable components.