jacobjwalters / cpu

Multi-cycle stack machine CPU

cpu

Multi-cycle stack machine CPU

Self-designed ISA, defining a multi-cycle CPU based on a dual stack machine (akin to the Forth mexecution model). Uses 6-bit bytes and 36-bit machine words. An ALU design is provided, based on a carry-select adder.

Designed and written over the course of my first year in sixth-form, from ~October 2018 to ~July 2019. There were many intermediary designs that got scrapped and reworked as I learned more about verilog and hardware design. Unfortunately, I wrote this before learning to use Git so that progress is lost to the sands of time.