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apb4_mux

APB4 Multiplexor

apb_vip

APB VIP (UVM)

axi-uvm

yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

books-1

ccia_code_samples

Code samples for C++ Concurrency in Action

cluelib

A generic class library in SystemVerilog

design-and-verification-of-apb-protocol

etl

Embedded Template Library

fiber

A portable single header C++ fiber function library for co-operative multitasking

jibster

kvasir

C++ Metaprogramming library enabling better static checking and register abstraction in embedded software

learnsystemc

Learn systemC with examples

litepcie_phy_wrappers

PHY wrappers for LitePCIe

mpl

Boost.org mpl module

nmigen

A refreshed Python toolbox for building complex digital hardware

real-time-cpp

Source code for the book Real-Time C++, by Christopher Kormanyos

simple_reg_model

System verilog register model for uvm testbenches.

state_machines

Adds support for creating state machines for attributes on any Ruby class

systemc

Core SystemC Library

systemc-compiler

This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

systemc-examples

A repository for SystemC Learning examples

systemrdl-compiler

SystemRDL 2.0 language compiler front-end

systemverilogassertions

Examples and reference for System Verilog Assertions

systemverilogreference

training labs and examples

themlbook

The Python code to reproduce the illustrations from The Hundred-Page Machine Learning Book.

tlm-of-a-pcie-rootcomplex-systemc

A transaction level model of a PCI express root complex implemented in systemc

uvm-python

UVM 1.2 port to Python

uvmc

Connecting SystemC with SystemVerilog

uvmreference

Reference examples and short projects using UVM Methodology

vpcie

implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture