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iamgzi's Projects
openwifi-hw
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
poc
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
pothoszynq
DMA source and sink blocks for Xilinx Zynq FPGAs
pp4fpgas
Parallel Programming for FPGAs -- An open-source high-level synthesis book
pp4fpgas-cn
中文版 Parallel Programming for FPGAs
public_atom_modules
通用的公共小模块
qpsk-vivadohls
QPSK system implemented using Vivado HLS
ramfile
Generic RAM blocks described in Verilog HDL for FPGA Verification.
satcommsystem-qpsk-ofdm-lsestimation-transionosphericchannel
MATLAB Imitation Modeling for the BER of the Satellite Communication System using QPSK and OFDM Modulation with LS Channel Estimation based on Pilot Signals in the Transionospheric Communication Channel with Rician Fading, Multipath, Frequency Selectivity and Limited Coherence Bandwidth
simulation_modulation
Matlab Simulation for DVB-S
turbocode
Turbo decoder using SOVA algorithm. Double binary, DVB-RCS code. MyHDL and VHDL models.
verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
verilog-axi
Verilog AXI components for FPGA implementation
verilog-axis
Verilog AXI stream components for FPGA implementation
verilog-ethernet
Verilog Ethernet components for FPGA implementation
verilog-lfsr
Fully parametrizable combinatorial parallel LFSR/CRC module
viterbi-decoder-in-verilog
An efficient implementation of the Viterbi decoding algorithm in Verilog
vivadohls-qam-sp605
High Level Synthesis FPGA example of QAM demodulator using Vivado HLS
wimax_ofdm
Partial Verilog implimentation of a WiMAX OFDM Phy
xilinx-openhw-contest
Xilinx OpenHW Contest Source Code
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