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I want to read a Verilog file using Lorina Verilog reader but I am getting parsing errors.

I am actually using Lorina as part of Mockturtle as I want to convert the input network read from Verilog file into a MIG network.

1. The following is my main.cpp

int main()
{
   std::string input_file, output_file, top;
   std::cout << "Enter the input verilog file name: "; // filename.v
   std::cin >> input_file;
   std::cout << "Enter the name of top module: ";
   std::cin >> top;

   diagnostics consumer;
   lorina::diagnostic_engine diag( &consumer );
   klut_network gate_network;

   if ( lorina::read_verilog( input_file, verilog_reader( gate_network, top ), &diag) != lorina::return_code::success )
   {
     fmt::print( "[e] Could not read input file `{}`\n", input_file );
     return -1;
   }
}

2. The input Verilog file for which the error occurs.

module full_adder(a, b, cin, S, Cout);
  input a, b, cin;
  output S,Cout;
  assign S = a ^ b ^ cin;
  assign Cout = (a & b) | (b & cin) | (a & cin); 
endmodule

3. Error messages or print-outs you see (if any) (preferably copy-pasted as-is).

[e] Diagnostic Message: `cannot parse expression on right-hand side of assign `Cout``
[e] Diagnostic Message: `cannot parse assign statement`
[e] Could not read input file `full_adder_1bit.v`

The statement assign Cout = (a & b) | (b & cin) | (a & cin); is not getting parsed and is throwing the above error as I understand.

Please help me understand the issue here. I tried raising an issue in Mockturtle(issue #624) but it was closed without the correct answer to this problem.

This should be lorina/aiger.hpp.

I got a compile error in C++17 mode with LLVM 6.0.0. The call to apply is ambiguous because there is a method in std applicable as well due to argument-dependent lookup.

In order to fix the issue, it is sufficient to replace apply in the following line by detail::apply.

A multi-output (sub-)module instantiated (once) in the top module triggers multiple times of on_module_instantiation. This is likely due to compute_dependencies being called for each output of the module in call_deferred.

Failing test:

TEST_CASE( "Multi-output module instantiation", "[verilog]" )
{
  std::string const verilog_file =
    "module FA( a, b, ci, s , co );\n"
    "  input a, b, ci;\n"
    "  output s, co;\n"
    "endmodule\n"
    "module top( x0, x1, x2, y0 );\n"
    "  input x0, x1, x2 ;\n"
    "  output y0 ;\n"
    "  wire overflow ;\n"
    "  FA adder1( .a (x0), .b (x1), .ci (x2), .s (y0), .co (overflow) );\n"
    "endmodule\n";

  lorina::text_diagnostics consumer;
  lorina::diagnostic_engine diag( &consumer );

  std::istringstream iss( verilog_file );
  simple_verilog_reader reader;
  auto result = read_verilog( iss, reader, &diag );
  CHECK( result == return_code::success );
  CHECK( reader._instantiations == 1 );
}

I'm having some difficulty parsing an ASCII AIG file that is not in a canonical form. Its inputs do not start from 1 and are not in numerical ascending order:

...
12
10
76
72
...

Its symbol table matches this ordering:

...
i0 symbol_of_12
i1 symbol_of_10
i2 symbol_of_76
i3 symbol_of_72
...

The 2007 AIGER TR has this to say about the symbol table:

Therefore a symbol table entry looks as follows:

[ilo]<pos> <string>

The position “pos” of the symbol denotes the position of the input, latch, or output, in the list of inputs, latches, and outputs respectively. It has to follow immediately the symbol type identifier without space.

My interpretation is that my AIG file is legally formatted. And in fact it was generated by another tool that claims to be AIGER compliant.

However, lorina appears to assume the number following the first character of a symbol table line is an index, not a position. The AIG parser calls on_input_name directly with this number as the index rather than cross referencing what index was at this position in the input/latch/output list.

Is my interpretation of the AIGER spec incorrect? Or maybe lorina is only intended to support canonical AIG files?

The files lorina/aiger.hpp and lorina/detail/utils.hpp are using std::vector without including it which can lead to problems, see, e.g., here:

https://travis-ci.org/lsils/mockturtle/jobs/523896213#L1586

static_truth_table and dynamic_truth_table do not implement operator== and operator!=, so code like tt1 == tt2 does not work. It seems you still can compare truth tables with something like the following (untested) code:

bool eq = true;
for (auto it = tt1.begin(), it2 = tt2.begin(); ; ++it, ++it2) {
  if (it == tt1.end()) {
    eq &= it2 == tt2.end();
    break;
  } else if (it2 == tt2.end()) {
    eq = false;
    break;
  }
  eq &= *it == *it2;
}

Is it possible to implement operator== and operator!= on these classes to avoid having to do this? It should be possible to do some template-based specialization to optimize these too.

OTOH perhaps I've misunderstood something and equality comparison makes no sense on these classes. In which case, I would be interested to learn of this too.

Have yall considered in your CMake a target for installation?

I know that it is header only and simple enough to copy the headers to where one wants but it often helps to have cmake installation setup in the CMake. At least when I use CMake for dependency install in an automatic way.

Am I missing something?

Thanks.

This issue is a reference to the pull request #30. Where a implemented feature integration with conan was presented.

I use the EPFL logic sythesis libraries quite frequently, if the feature is approved I can implement it to the other libraries as well.

Best.

How do you run a bench file with lorina? Do you have to run it to read the bench file line by line? We downloaded the lorina library and are trying to run it to read the bench file and it isn't working. The bench files we are trying to read are found here. http://www.pld.ttu.ee/~maksim/benchmarks/iscas85/bench/
Thank you.

Hi there,
I'm new to Lorina, I'm wondering how can I read in Verilog files and convert the AST to And-Invert Graph (AIG)?
Thanks a lot in advance!