howardlau1999 / yatcpu

Yet another toy CPU.

YatCPU

简体中文 | English

YatCPU(Yet another toy CPU) is a simple three-stage pipeline RISC-V implementation written in Chisel 3 HDL with support for AXI4-Lite, featuring its painless hands-on experience and VGA output for fun.

You can play Tetris on your own CPU!

You can also run an NES emulator!

Heavily inspired by tinyriscv, this project is still in its very early stage and under active development. We are looking forward to your feedback and contributions!

Development Plans

• L1 I-cache and D-cache
• Branch predictor
• Run Yat-sen OS RISC-V
• RV32M
• Pass RISC-V compliance test
• Run CoreMark benchmarks

Prerequisites

You

• Basic knowledge of digital logic and design principles
• Basic knowledge of C/C++
• (Optional) A FPGA development board

Your computer

• Windows 10 or higher / Linux (Debian, Ubuntu, WSL1/2 or other distros) / macOS
  • We have tested on Windows 10 and WSL Debian 11
  • macOS is able to run the software simulation, but unable to write FPGA boards
• Java 8 or higher
• Scala 2.13.8 (not 3)
• sbt
• (Optional) Latest Verilator
• (Optional) Vivado 2020.1 or higher

Getting Started

Please refer to YatCPU Docs for more documentation.

yatcpu's Issues

Schedule processes when the hardware timer ticks

The very first step towards a working minimal operating system is the ability to do some initialization work after booting up and handle interrupts where it can have a chance to schedule and switch processes.

To achieve this, we should

• Write the entry function which does all the initialization work including initializing necessary data structures and setting up interrupt handler
• Define a minimal structure of PCB(Process Control Block)
• Implement the context switch function
• Implement a very basic scheduler
• Call the scheduler and switch to target process when the hardware timer ticks

Is it necessay to have a HDMI display modual for Pynq-Z1 which has no VGA ?

The Pynq-Z1 has no VGA and we just want to use the FPGA part of the board. So if we want to display something , we need to write a HDMI display modual with chisel like the vgadisplay module.

调整 src 目录下的代码结构

考虑到以后可能会移植到 basys3 之外不同的板子上，是不是把 CPU 本身的代码和到特定板子的移植代码分离比较好，比如再建一个 /src/fpga 目录

Add RV32I compliance test

Write tutorial on compiling and linking executables

Implement the 5-stage pipeline with the bypass feature

Run CoreMark benchmark

Implement micro-codes

Support CLINT interrupt controller

Implement CSR registers

Explore RV32V vector instructions

Support AXI-Lite bus protocol

Implement register renaming

Register renaming is a common feature among modern processors; it can improve throughput by reducing structure hazards.

We need to keep track of the status of physical registers and assign free registers to logical registers when needed.

Load the executable from Flash

It is painful and time-wasting each time we want to load a different executable because we need to go through the whole process of synthesis and implementation again and again.

Sometimes the only difference is the executable itself, so it would be time-saving if we could load the program from a programmable Flash such as the onboard QSPI Flash.

Write a minimal shell

After we implement a minimal process scheduling mechanism in #13 , we can write a minimal shell which reads and parses user input from UART and performs the corresponding operations.

Use SYsU instead of C as test code

To archive the goal "run your OS compiled by your compiler on your CPU", it's elegant to use SYsU instead of C as test code.

Implement MMIO

Support integer multiplication and division

This feature involves designing a pipeline co-processor to perform integer multiplication and division. The co-processor may stall the pipeline during the calculation and write back the result to destination register.

Implement L1 caches

The processor is now fetching instructions and doing memory operations via a shared bus. It can be seen that the pipeline is mostly stalled due to slow bus operations. Modern processors offer caches to fill the gap between the core and the bus.

Although we have a von-Neumann architecture CPU, L1 caches are usually split into I-cache(I$) and D-cache(D$) for instructions and data respectively.

These caches are commonly set-associative and implemented as SRAMs. The caches should keep record of cache line status and request bus for memory operations if needed.

Implement branch predictor

Weekly Catch-up #5

• Passed RV32I compliance test

Weekly Catch-up #4

• Add HDMI display and Top module for Pynq-Z1
• Update Chisel3 to 3.5.1

Weekly Catch-up #2

2022.1.9~2022.1.15 Summary

• No progress due to final exams.

Weekly Catch-up #1

The developers will keep you posted by summarizing the progress made in the past week.

调整 src 目录下的代码结构

考虑到以后可能会移植到 basys3 之外不同的板子上，是不是把 CPU 本身的代码和到特定板子的移植代码分离比较好，比如再建一个 /src/fpga 目录