hneemann / digital Goto Github PK

So far, no resistors are available. This makes it impossible to simulate some CMOS circuits (See #22, #29)

In CMOS circuits short circuits often occur for very short time. During this time a large voltage drop occurs at the conductive FET and a large current flows. However, different voltage levels may exist on both sides of the FET because of its residual resistance. After a short time, one of the short-circuiting transistors opens and the current disappears. This produces a sharp current peak at the moment of switching.
In digital, a conducting transistor has no resistance. Source and drain are shorted out in the conducting state and therefore can not have different voltage levels. This causes a signal change to have no effect. Source and drain have always the same voltage level. The transistor which would open due to the different voltages remains conductive. In this case, an error message appears and the simulation is terminated.

Therefore, the simulation of some FET circuits does not work properly. To solve this problem, it must be allowed for a transistor to have different voltages at the source and drain even in the conducting state. This means that the residual resistance must not be zero.

This problem is related to the implementation of real diodes.

To overcome the issues caused by the missing residual resistance, the FET has an option to make it unidirectional. This is an ugly hack, but it helps to make more circuits work.

It would be nice if the component tree view state (visible or not) was saved, so that people using it do not have to make it visible upon every launch.

Zum Simulieren einer Schaltung benötige ich einen Zähler der mindestens 4 Bit BCD hochzählen kann (ausgehend von einer Signalquelle).
Ich habe das behelfsmäßig mit Flip-Flops umgesetzt, es wäre aber hilfreich einen entsprechenden Baustein direkt nutzen zu können.

When starting analysis for a circuit, the following message appears if the input are not labeled. A similar message also appears of the outputs are not labeled.

This is confusing as the circuit actually has inputs, they are just not labeled. The message should be changed to reflect that the inputs and outputs are not labeled.

In attributes dialog address bit size takes effect after closing dialog. That is confusing when "Edit" is used before closing the dialog.
Before the "Edit" button opens the "Data" dialog a message box should allow the user to accept the current setting.

Can not work with 32 address bits. Only one line of the memory is shown in "Data" dialog.

With data bits 25 and address bits 25 "Edit" do not open the "Data" dialog.

The data dialog shows only 6 chars per cell. So working with data bit sizes greater 24 is a pain. Each time the "Data" dialog is opened the column size of the interested cells have to be changed manually.

In the Edit Circuit Attributes window, one of the two checkboxes (DIL package, Modification Locked) appears in the Background Color section. The checkbox appears only after moving the mouse over the Background Color section. The checkbox that appears is the last one over which the mouse moved over.

I just tried running Digital under Fedora 25 with Gnome 3.22.3 and Wayland and unfortunately the DPI scaling isn't working.

Tested in v0.13-157-g21f7c03
CTRL-S doesn't work in Digital but works in other apps.

Hi just a quick note to let you know that the latest release has no JAR file in either of the archives, but your read me on the main repo page tells folks that it does and is ready to run without building.

All that exists in the Distribution folder is:
Digital.exe
ReleaseNotes.txt
Version.txt
Assembly.xml
l4jconfig.xml

When digital is run it fails and stops with a message it cannot find Digital.jar

1. The error message says the same thing twice:
   

2. A large text object is put on the schematic. This is unnecessary as there is already an error message pop-up giving the same information to the user.
   

At the moment an input pin can not have "high z" value by default.
If a circuitry depends on that state, it may not start.

Hallo,

das Problem betrifft hauptsächlich Macs, da man fn + backspace drücken muss um ein entfernen zu betätigen, aber auch auf Windows-Laptops würde dies die Usability verbessern.

I'm trying to add test cases for a new IC. I'm not sure what I'm doing wrong, but I get the following error message when running the tests. The input pin labels match the names in the test cases.

• Drawing wires and deselecting the wire tool can be hard on a HiDPI screen. Clicking while the mouse is moving will trigger the selection box instead of the wire tool. Right clicking while the mouse is moving will move the schematic instead of triggering the deselect action. If you consider that 1px is the smallest mouse movement that is possible, then a much smaller physical movement is needed on a HiDPI monitor to move the mouse by 1px than on a regular HD screen at the same mouse sensitivity. On my 4k screen, I noticed that I see the selection box appear briefly when I try drawing a wire and it doesn't work. If I stand very still while I click or right click, everything works as intended. So what is considered a mouse movement that alters the non-moving behavior should probably be scaled with the pixel density.

• If the mouse moves slightly while selecting a component in the tree view, then the component is selected in the tree (greyed out) but the mouse is not moved back to the schematic and the component placement tool is not activated. When this happens, the tree view looks like this:
  

• The tree view issue happens even on a regular HD monitor, probably because of the larger mouse movement required to reach the selection zone, although less frequently than on a HiDPI monitor. I suggest removing the mouse movement detection in the tree view as there is no alternate behavior when moving the mouse anyway.

Since these basic gates exist with more than two inputs (implemented as a cascade of binary XOR), it would be nice to be able to adjust the number of inputs in Digital.

Adding spaces or certain special characters (e.g. è, ç, %) to the Digital folder name prevent the Library sub circuits from being imported. This was tested under Windows 10.

Steps to reproduce:

1. Download Digital V 0.13
2. Extract the zip archive
3. Start Digital
4. Notice that the Library sub circuits are imported correctly
5. Exit Digital
6. Rename the folder to "Digital 0.13"
7. Start Digital again
8. Notice that the Library sub circuits are not available

It would be nice to have a hint when our work is saved, such as greying out the save buttons.

In order to run the simulation, Digital requires all inputs on DIL packages to have a connection to a definite state. I understand how it is necessary to have all inputs connected for the simulation to be able to establish the state of the outputs. However in practice, when using ICs in DIL packages, sometimes some outputs and their associated inputs remain unconnected because they are not needed. For example, you might only need to use one of the two flip-flops on a 74112.

This makes it impossible to make circuits in Digital that look like what you would really do. For example, in practice, a circuit using a 74107 to toggle an output would look like this. The inputs and outputs of the second flip-flop are not connected but it works just fine.

While in Digital you need to connect all other pins to an arbitrary value, which makes it look like this:

Would there be a way to remove the requirement to have all inputs connected for DIL packages? In order to avoid dealing with undefined states, this could be effective only if the associated outputs are also not connected. I haven't seen the code so it might not be that simple, but I'm thinking that if all outputs of a circuit inside a DIL are not connected, you could simply ignore that circuit during the simulation.

I just feel the additional wires that need to be connected are causing unnecessary clutter in the schematics, take additional time to setup and might be confusing for the students.

Simple version
Allow editing attributes when selected components are from same type

• "Reset all diodes and FGETs" is not needed anymore. The selection allow a group wise reset and set

Advanced version
Allow editing identical attributes when selected components are from different types.

• fast changing of "Data bits" for all components

Maybe all attributes need internal parameter "allow group wise edit" to define which parameter support this feature (not for Label, Description ...)

When changing settings that require a restart, a warning is shown to the user explaining that a restart is required. However, when changing the "Use IEEE 91-1984 shapes" setting is changed, no warning is displayed even though a restart is required.

Although I have an intuition about what this probably means, it really isn't clear from the documentation.

Allow copying the content of the info dialog (Help>About) enables a easy way to add version information to an issue.

One should clearly see if a connection is a simple wire or a bus.
Color discrimination is not sufficient. Maybe one could draw several parallel lines?

I tried create CMOS full adder cell from PSX CPU and encount error. When I try switch pin B or C in given circuit from 0 to 1 not order of update of elements rise error.

At picture there are full adder on left and simplest part that generated error on the right.

If i set default state from the start - circuit updates correctly, but it fails again if I switch from 0 to 1.

This is something that I love in Logisim but can't do in Digital. While it is purely a convenience feature, it helps make circuits a lot more compact. It is also less wires to connect.

Logisim implements this with a drop-down menu for each input (inverted yes/no), but if you want to keep the UI simple and compact a simple text field where a comma/space separated list of input to invert can be provided would work very well.

p.s. I will stop sending you lots of issues soon ;- ) I worked all day in Digital yesterday hence all the issues, but now I think I have pretty much found all I could. Thanks for your work and your support!

It would be useful to be able to skip pins in the Pin Wizard for unused pins such as GND and Vcc.

Suggestion: Right clicking could skip to the next pin number.

Der einzige Weg, den ich gefunden habe, um "Leitungen" zu löschen ist, diese über Aufziehen eines Fensters zu selektieren. Dies ist nicht immer möglich. Bei einer Leitung von der links und rechts weitere abgehen selektiert man automatisch auch die angrenzenden.
Es wäre vorteilhaft, wenn man durch einfachen Klick in eine Leitung diese selektieren könnte. Bisher erzeugt dies einen Abzweig von dieser Leitung.
Eventuell wäre es dann in dem Zuge sinnvoll separate "Auswählen" und "Verbindungsleitung zeichnen"-Werkzeuge anzubieten.

When a circuit error happens (such as no value set for an input), a message is displayed and a circle is displayed around the affected component. However, if the component is outside the view of the schematic, then the user will not be able to see which component was affected. The x, y coordinates are provided in the error message but these are not useful for the user since there doesn't seem to be a way to display them in the schematic.

I suggest centering the schematic view on the affected component when such an error happens (but make sure the pop-up is not over the component). I would also remove the x, y coordinates from the error message since they are not really useful.

Also, making the error circle around the component bright red would make it more obvious and different from the regular selection circle.

On a high DPI screen, the text, icons and buttons are very small and hard to read.

Here is a screenshot of the settings window. The font size used for the title is scaled properly and is easy to read. However everything inside the window is much smaller than it should be and hard to read.

This was tested under Windows 10. Many (but not all) valid characters have been tested and only the following two are known to cause the issue:

Character that causes a Java Exception on startup: !
Character that prevents Digital from starting but does not cause an exception: ;

Version: v0.12.1, commit 93a576c2e193caa54b9e29ae8341af42919f9cca
OS: macOS Sierra, 10.12.4 - MacBook Pro, Retina 15'

Die Baumansicht der Bauteile wird angezeigt wenn man unter Ansicht diese Option aktiviert. Sie öffnet sich aber zu klein und man kann die Größe nicht immer verändern.

Die Veränderung dieser "Vertical Bar" funktioniert nur bei jedem ca. fünften Versuch (beim verschieben nach rechts). Wenn man die Bar nach links verschiebt klappt es meistens, aber auch nicht immer.

Auch werden die Icons der Bauelemente nicht korrekt skaliert - man kann die Elemente der Baumansicht nicht voneinander unterscheiden.

Screenshot:

I'm willing to build a computer with Digital but as far as I know it will not be able to write anything to disk because the only persistent memory we have is ROM.

Would it be possible to add a "hard drive disk" component tied to a specific file or something equivalent ? A nice start would simply be to be able to copy/paste the whole data of a RAM module to manually save or load the content of writable memory as Logisim allows for example.

If a file is opened the library path is set to the folder of the opened file. All files in and below that location are used as library files, which means you can include them by the components menu.
This avoid the dealing with additional library paths, to include components. You also can simply zip a folder and you have all the components needed to work with the circuit.
But in some cases this behavior is confusing to the user (See #32, #38). Maybe the handling of libraries should be changed.

Digital stalls when pressing OK in the test window if the last line of the test cases is a comment.

For example:

~U/D	~CE	~PL	CP	D0	D1	D2	D3	Q0	Q1	Q2	Q3
# Pre-Load & Hold
X	X	0	C	1	1	1	1	1	1	1	1
X	1	1	C	1	1	1	1	1	1	1	1

# Count Down

Having a link to the full documentation pdf within Digital would allow users to quickly open the documentation instead of having to browse their file system. Also, people may not know the documentation exists unless they look into the Digital folder. Having a link would make it easier to discover.

The link could be added in the help menu, right under Components

Logisim allows setting the trigger for flip-flops to rising or falling edge. It would be nice to have the same option in Digital.

For implementing XOR, you can use 6 transistors, two of which are transmission gates. It would be great if you could add those!

After working some more in the latest version, I would suggest the following:

Shortcuts when a basic gate is selected:

• PLUS (+) : Increase the number of inputs by one
• MINUS (-) : Decrease the number of input by one

For wire placement (which, by the way, is much improved in the latest version!):

• When pressing CTRL+Click to select a wire while in wire placement mode, get out of wire placement mode and select the wire instead. It happened a few time that I was trying to select a wire and it wouldn't work because the wire placement mode was active. When it happens, it can hard to see since the wire being placed is over the wire you're trying to select. CTRL+Click should have the priority since it is a more elaborate command which can hardly be made by mistake.

For components that have a label:

• When you open the component properties, it would be nice to give focus to the Label field, so that you can just type right away and press enter to confirm the new label name. At the moment, the Rotation field has the focus by default. However, rotation can be done with the R shortcut directly in the schematic, so you will rarely want to open the properties dialog to change the rotation. Giving the Label field focus by default would make more sense.

Ich hoffe Issues in Deutsch sind OK. Andernfalls schreibe ich in Zukunft in Englisch.

Bei meiner ersten Verwendung von "Digital" habe ich intuitiv versucht begonnene Aktionen, wie das Zeichnen von Linien, via "Esc" abzubrechen, was leider nicht möglich ist. Mein Vorschlag wäre, die Taste dafür nutzbar zu machen.

First of all, I'd like to say that it is great project and I like it very much. But i'm getting frustrated every time I used the program :(

It is pain to move wires and components around once I've place them. Single left click on component for moving it right away - it's very hard to get used to. When I try to select group of components that already wired up, it is nearly impossible without touching connected wires (for example, if I want to select and delete them, it can be done only individually for every single component). No shift + click combination to combine selection.

Single left click to place wire - it's not what I need in most cases. I am expecting Pointer tool be active by default (like in Logisim).

And one more thing: I cannot find how to enable grid dots in document, it difficult to me to wire thing up without grid.

Anywat, Digital is so awesome and intuitive after using Logisim, thank you!

In "Measurments" dialog it is possible to open "Data" dialog which shows the content of a memory. The content is correct updated during simulation. When simulation is stopped the dialog stays opened. After starting the simulation again the content is not updated anymore. The dialog has to be closed and reopened.

T flip-flops should have a T input that enables the toggle function of the flip-flop.
https://en.wikipedia.org/wiki/Flip-flop_%28electronics%29#T_flip-flop

While some real world T flip-flops may omit the T input, having the input in Digital would be better since it can be hooked to a constant when not needed and would allow simulating T flip-flops that do have the T input without using other logic components.

Is it possible to create bidirectional pins that can be used an IN pint and as OUT pins simultaneously? This is usual for data buses.

The specific use case I'm thinking of here is people doing a "Build everything from NAND or NOR like in the nand2tetris course", who would like to use their own gates rather than the built-ins, but would still like the correct IEEE symbols.

If you open two instances, create a faulty circuit in one instance, you can't start the simulation in the other instance anymore.

Steps to reproduce:

• Save a circuit named test.dig in that contains only basic parts under \foo and close digital
• Put the 74116.dig file in \foo\a and in \foo\b
• Open test.dig and try adding a 74116 IC to the schematic. This will trigger an error because the same file exists twice in the import path.
• Dismiss the error pop-up and delete the part (large error message placed in the schematic) so that no trace of the 74116 part exists.
• Try saving the document again and notice that the error pop-up appears again.

Expected results: Removing the error causing part from the schematic should prevent the error message from appearing.

I would suggest implementing the following shortcuts:

• CTRL+S : Save
• CTRL+X: Cut. Cut and paste would be different from selecting and moving since the cut functionality would disconnect the wires.
• SPACE : Start/Stop the simulation

Version: v0.12.1, commit 93a576c2e193caa54b9e29ae8341af42919f9cca
OS: macOS Sierra, 10.12.4 - MacBook Pro, Retina 15'

Die Icons in den Menü-Elementen (Im dropdown) werden nicht korrekt skaliert und machen das manche Menü-Einträge viel höher sind als solche ohne Icon.

Up to now only export to VHDL is available.

At the moment I use the VHDL export only as a vehicle to run a circuit created with Digital on an FPGA, without explaining the VHDL code itself further. This is similar to the export of a JEDEC file for a GAL16v8: The JEDEC file is necessary to program the GAL, but its content is not considered further.
From this point of view it does not matter if VHDL or Verilog is used.

If someone wants to use an export to VHDL or Verilog in another way, I would be glad to hear about it. In my opinion, an HDL export is not suitable to teach the HDL itself. This is because the generated code uses only a small fraction of the HDL, and the direct translation of all components to an HDL entity is not always optimal. Humans would use an HDL in a different way.

The custom block width seems to be fix. It should depend on the input and output with the longest label to avoid overlapping labels.