hazooree / lenet-cnn-accelerator-hardware-for-fpga

An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017

Systolic Array Based LeNet-CNN-Accelerator-for-FPGA

An open source Verilog Based LeNet-1 CNNs Accelerator for FPGAs. Trained weights of the model are in "W.mem" file in "Other-files" directory.

for more details on theory you can refer to https://arxiv.org/ftp/arxiv/papers/1901/1901.04986.pdf.

Please cite as: {Hazoor Ahmad, Muhammad Tanvir, Muhammad Abdullah, Muhammad Usama Javed, Rehan Hafiz, and Muhammad Shafique. "Systimator: A Design Space Exploration Methodology for Systolic Array based CNNs Acceleration on the FPGA-based Edge Nodes." arXiv preprint arXiv:1901.04986 (2018).}

How to run

Requirement:

Vivado 2017.1 or above (as I have used)

Procedure

1. Make a new project in vivado
2. Add files (Conv3D.v, FC.v, LeNet.v, MACC.v, Multiplication.v, PE.v, PE_Array.v, max2.v, softmax.v) from folder (Verilog-Source-Files) to your project as 'design sources'.
3. Add file (tb_LeNet.v) from folder (Other-Files) to your project as 'simulation sources'.
4. Add files (I0.mem, I1.mem, I2.mem, I3.mem, I4.mem, I5.mem, I6.mem, I7.mem, I8.mem, I9.mem, W.mem) from folder (Other-Files) to your project as 'design sources'.
5. Change inputs from line 56 of LeNet.v in folder (Verilog-Source-Files). [like I4.mem instead of I3.mem]
6. Before simulation confirm simulation time should be more than 10000ns to do it go to: Project Manager -> Settings -> Project Setting -> Simulation -> Find Simulation tab -> change xsim.simulate.runtime from 1000ns to 1000us

Alternatevly: You can directly run this command in 'tcl console'

set_property -name {xsim.simulate.runtime} -value {1000us} -objects [get_filesets sim_1]

7. Simulate and get the desired result

Details of work

LeNet-1 Network

LeNet-1 Architecture for handwritten digit recognition is given by

LeNet-1 Model Summary

Systolic Array Based Hardware Architechture Design

Controller

Convolution Layer PE Array (5X6) Micro-Architecture

Processing Element (PE) and MACC Units

Fully Connected Layer Micro-Architecture

Fast Softmax Micro-Architecture

Results Before Softmax Layer (Keras Vs Vivado)

lenet-cnn-accelerator-hardware-for-fpga's Issues

help

How can I enter test data?