gzyide / sysvdevenv

Template RTL development environment for SystemVerilog

SysvDevEnv

Easy to use RTL development environment for SystemVerilog.
Vivadoやyosys, iverilogを用いたSystem Verilogの開発環境です。
ついでにvimでの開発も考慮し、SystemVerilogの文法チェック環境も用意してみました。

Directory

For more details, see comments of each files

• rtl

  • Directory for SystemVerilog source files

• include

  • Directory for Verilog or SystemVerilog include files

• test

  • Directory for test vectors and test utilities
    • Scripts
      • testvec.sh :
        Execute testvec.sh to start RTL/Netlist Simulations
      • target.sh :
        Select DUT (Design Under Test) in this file
      • module.sh :
        Describe dependent files in this file
      • sim_tool.sh :
        Select Logic Simulators in this file
      • clean.sh :
        This scripts eliminates logs and binaries created by simulators
    • directory
      • tb Testbench written in SystemVerilog
      • include Include files for test
      • xilinx Simulation and debug environment for vivado
  • For more details, see README.md in test/README.md directory

• syn

  • Synthesis script for yosys and Vivado
  • If you would like to use systemverilog, Yosys-systemverilog instead of Yosys is recommended

• sv2v

  • Converts SystemVerilog into Verilog using sv2v
  • If you want to test your designs with iverilog or synthesize them with Yosys, this might be helpful!

• syn (Coming soon...)

  • Directory for logic synthesis scripts for ASIC
  • For more details, see README.md in syn directory

• fpga (Coming soon...)

  • Directory for logic synthesis and P&R scripts for FPGA
  • For more details, see README.md in fpga directory

• vim

  • Enviroment for syntax checking using vim syntastic plug-in
  • See vim/README.md for more information.