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practical-uvm-step-by-step

This is the main repository for all the examples for the book Practical UVM

risc-v-pipeline

SystemVerilog realization of RISC-V processor

riscsoc

RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核

riscv-pulpissimo-fpga-implementation-for-zcu102

rtl-design-for-fpga

sdram-verification

This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed by Dinesh in Opencores.org

serialchart

一个很好用的串口示波器。

source-repository

sram

Simple sram controller in verilog.

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

systemverilog

This repository contain all trainig codes and project used SystemVerilog language

twireserintrfc

A verification test case for a master implementation of the Two-Wire Serial Register Interface based on Systemverilog and UVM.

ustc-rvsoc

FPGA-based RISC-V CPU+SoC.

uvm

优秀的UVM项目整理

uvm-components

Contains commonly used UVM components (agents, environments and tests).

uvm-python

UVM 1.2 port to Python

uvm_verification

Examples with UVM

uvm_verification_for_p2s_data_converter

为了学习UVM验证相关知识，需要动手尝试实际的项目。作为一个初学者，难以接触到实际的项目，于是我从夏宇闻老师的《Verilog数字系统设计教程》一书中，挑选出一个简单的小设计，作为我的验证对象，并围绕它编写了UVM验证环境。

uvmprimer

uvmprimer-1

Contains the code examples from The UVM Primer Book sorted by chapters.

uvvm

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

verification-of-single-port-ram-with-systemverilog-and-uvm-

vnote

A pleasant note-taking platform.