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10-gigabit-ethernet-mac-verification

Verification of a 10 Gigabit Ethernet MAC using a SystemVerilog OOP Testbench

80x86

80186 compatible SystemVerilog CPU core and FPGA reference design

ahb-lite-verification-in-systemverilog

EE-599f SoC SystemVerilog Final Project

amba_apb_sram

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

amba_axi_ahb_apb

arm_cortex-m3

该项目依据全国大学生集成电路创新创业大赛“ARM杯”赛题要求，在FPGA上搭建Cortex-M3软核、图像协处理器，并通过OV5640摄像头采集车牌图像，实现对车牌的识别与结果显示。项目基于Altera DE1 FPGA搭载Cortex-M3软核，依据AHB-Lite总线协议，将LCD1602、RAM、图像协处理器等外设挂载至Cortex-M3。视频采集端，设计写FiFo模块、SDRAM存储与输出、读FiFo模块、灰度处理模块、二值化、VGA显示等模块。最终将400位宽的结果数据（对应20张车牌）存储在RAM中，输出至AHB总线，由Cortex-M3调用并显示识别结果。

async_fifo_verification

Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.

awesome-dv

Awesome ASIC design verification

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

cocotb-coverage

Functional Coverage and Constrained Randomization Extensions for Cocotb

core_ftdi_bridge

FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge

cores

Various HDL (Verilog) IP Cores

deeplearningonfpga

design-verification

UVM and Systemverilog based test benches for functional verification of a RAM module

dpi_tutorial

e200_opensource

The Ultra-Low Power RISC Core

ethernet-packet-loopback-design-verification

Ethernet packet loopback design verification using SystemVerilog

extremedv_uvm

UVM resource from github, run simulation use YASAsim flow

fpga-dac-r2r-pwm

FPGA-based 14bit DAC with resistance network and PWM.

fpga-ftdi245fifo

FPGA-based USB fast communication using FT232H/FT600 chip.

fpgasimulation

function_generator_systemverilog

A limited yet very cool function generator implementation using look up tables and PWM

gaia

Generate UVM testbench framework template files with Python 3

gen_amba

gen_amba-1

AMBA bus generator including AXI, AHB, and APB

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

learning-systemverilog

learning notes of SystemVerilog与功能验证

mipi_dsi_bridge_fpga

Source code of MIPI DSI Bridge Published on https://www.circuitvalley.com

openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware