The bigspicy's discuss from google

  File "./bigspicy.py", line 24, in <module>
    import circuit_writer
  File "/media/karim/Elements/work/bigspicy/circuit_writer.py", line 24, in <module>
    class CircuitWriter():
  File "/media/karim/Elements/work/bigspicy/circuit_writer.py", line 27, in CircuitWriter
    circuit.Port.Direction.INPUT: circuit_pb.Port.Direction.INPUT,
AttributeError: 'EnumTypeWrapper' object has no attribute 'INPUT'

Steps to Reproduce the Problem

clone the repo
sudo apt install -y protobuf-compiler iverilog
pip install -e ".[dev]"

git submodule update --init   # Make sure we pull from Vlsir/schema-proto the
                              # first time.
protoc --proto_path vlsir vlsir/*.proto vlsir/*/*.proto --python_out=.
protoc proto/*.proto --python_out=.

run the script with any input output

Specifications

Version:
repo version:

v0.0.1

also happens with latest commit as of this post date
python version:

❯ python3 --version
Python 3.8.10

Platform:

Ubuntu 20.04.3 LTS

Failure when spice netlist has a disconnected pin

When trying to import some sky130 gate level verilog, bigspicy fails with:

NotImplementedError: Is this supposed to be a disconnection?

The problem is a tie cell, in which a disconnected pin is expected (both LO and HI are rarely used together). A verilog test case:

module test (
  VGND,
  VPWR,
  hi
);
  input VGND;
  input VPWR;
  output hi;

  sky130_fd_sc_hd__conb_1 const_hi (
    .HI(hi),
    .VGND(VGND),
    .VNB(VGND),
    .VPB(VPWR),
    .VPWR(VPWR));

endmodule

And the spice:

.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
R0 VGND LO sky130_fd_pr__res_generic_po w=480000u l=45000u
R1 HI VPWR sky130_fd_pr__res_generic_po w=480000u l=45000u
.ends

run with:

./bigspicy.py --import --verilog test.v --top test --spice_header test.spice --dump_spice test_out.spice

Show an example using Xyce running on multiple machines using MPI

As BigSpicy simulations can get large pretty quickly, it would be great to see an example of Xyce running on multiple machines using MPI (preferrable on Google Cloud Platform).

Set up automatic publishing to PyPi

Actually describe what BigSpicy does at the start of the README

Currently it is unclear what BigSpicy does and why I would want to use it.

Verilog support for continuous assignment

I'm not sure if simple continuous assignments are valid structural Verilog, but OpenROAD (well OpenSTA) does use them in some cases, so it would be nice to support it:

// Verilog "ports" are not distinct from nets.
// Use an assign statement to alias the net when it is connected to
// multiple output ports.

Steps to Reproduce the Problem

cat << EOF > testmodule.v
module testmodule (
    in,
    out
);
    input in;
    output out;

    assign out = in;

endmodule
EOF
./bigspicy.py --import --verilog testmodule.v