gmejiamtz / sdram_controller_generator

A Chisel hardware generator for SDRAM controllers from their datasheets

 

SDRAM Controller Generation

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About

In this project, we provide a Chisel generator for SDRAM controllers. Users will supply a .json representation of their targetted SDRAM's datasheet to provide timing values and other parameters such as address bus size and frequency. Templates are provided in the templates directory and provides more information on .json file formatting.

Usage

To use this generator follow the steps below:

Step 1

Clone the repo:

git clone https://github.com/gmejiamtz/sdram_controller_generator.git

Step 2

Supply your config.json file and provide the generator its path to generate SDRAMController.v:

cd sdram_controller_gen
sbt "run $PATH_TO_CONFIG_FILE"

Step 3

To test simply do the following commands:

cd sdram_controller_gen
sbt test

Tests at the moment only test for initialization of an MT48LC1M16A1 Micron SDRAM. More will be added soon!

To Do List

Targetting Micron MT48LC1M16A1 SDRAM - 512K x 16 x 2 banks

1. Build SDRAM controller state machine - In Progress - Init and Read(CAS of 1,2, and 3) States are verified, Write State in current testing

2. Build SDRAM controller model - In Progress - Mostly complete, needs more rigorous testing, proper decay parameterization

3. Generate tests for MT48LC1M16A1 controller - In Progress - Analog Connection posing issues with ChiselTest thus need to write Verilog Testbenches by hand and use Verilator and Icarus-Verilog for simulations

4. Build Main program to generate Verilog - Parsing is done, need to rewrite Parameter case class to take in Map of String to Int

🔨 Tools

The following tools were used in this project:

• Chisel 3.6
• Yosys Open SYnthesis Suite
• Verilator

📝 License

This project is under license from MIT. For more details, see the LICENSE file.

Made by Gary Mejia and Joaquin Ortiz for CSE 228A - Agile Hardware Design

 

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