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progetto_reti_logiche_2021-22's Introduction

Progetto Finale di Reti Logiche 2021-22

License: MIT

Voto: 30 e lode

Descrizione generale

Lo scopo del progetto era quello di descrivere in linguaggio VHDL e di sintetizzare un componente hardware che legga i dati dalla memoria, effettui una codifica convoluzionale con rapporto 1/2 ed infine scriva il risultato in memoria.

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