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View Code? Open in Web Editor NEWD-RAL - Device Register Access Layer
License: MIT License
D-RAL - Device Register Access Layer
License: MIT License
Consider the following example:
device:
name: TEST_DEVICE
description:
peripherals:
- name: PERIPHERAL
description:
address: 0x00
registers:
- name: TIM1
description:
offset: 0x00
reset_value: 0x00
fields: []
- name: TIM3
description:
offset: 0x02
reset_value: 0x00
fields: []
The TIM3
register will be accessible from C++ code as D-RAL register and from the register bank TIMx
.
peripheral::tim3::read();
// OR
peripheral::timx::read(3); // Should this be 2 or 3? There is TIM0 in this example, but there could be
TIMx
is defined as follows:
using timx = TimxBankReg<BaseAddress + 0x0000, 0x0002>;
The offset, 0x0002, is calculated as the difference between TIM3
and TIM1
, which is incorrect.
Using tim3::read()
will read from address 0x02, which is expected, but using timx::read(3)
reads from address 0x06.
Registers whose name differs only by a number at the end are automatically treated as register banks by D-RAL. This makes it impossible to generate some register combinations.
Take this exemplary registers from ENC28J60 Ethernet controller from Microchip:
Address | Name |
---|---|
00h | MACON1 |
01h | Reserved |
02h | MACON3 |
03h | MACON4 |
It can be represented in YAML format as so:
device:
name: ENC28J60
description: Stand-Alone Ethernet Controller with SPI Interface
peripherals:
- name: MAC
description: Medium Access Controller Registers
address: 0x00
registers:
- name: CON1
description:
offset: 0x00
reset_value: 0x00
fields: []
- name: Reserved # This register can be removed; doesn't affect the result
description:
offset: 0x01
reset_value: 0x00
fields: []
- name: CON3
description:
offset: 0x02
reset_value: 0x00
fields: []
- name: CON4
description:
offset: 0x03
reset_value: 0x00
fields: []
Using a custom adapter as described in Wiki yields the following result:
> python3 my_dral.py enc28j60.yaml .
ERROR: Register banks offset not consistent: [0, 2, 3]
Registers dump:
[
<dral.types.Register object at 0x7ff99eb52210>,
<dral.types.Register object at 0x7ff99eb5cd10>,
<dral.types.Register object at 0x7ff99f143650>
]
The CON
registers are treated as register bank and because CON2
is not present in the device a register bank cannot be created as the offsets are not consistent (offset of 2 between first pair of registers, and offset 1 between the other ones).
There is a TODO to refactor banks support so maybe this issue is known.
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