This project forked from qedady/risc-v-processor
This project is a co-work between Amer Elsheikh and Gehad Ahmed to build a fully functional RISC-V processor using Verilog as part of the computer architecure course at the American University in Cairo.
The processor is fully pipelined and handles all types of hazards correctly while working with a single memory for reading and writing. The processor hanldes all RV32I instructions in addition to RV-32M standard extension.
More deails are in the technical report and the schematic
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