gbert / openwrt-misc

openwrt-misc

Miscellaneuos OpenWrt stuff

openwrt-misc's Issues

Use 728-MIPS-ath79-add-gpio-irq.patch

This is more a question than an issue.
I've added your patch 728-MIPS-ath79-add-gpio-irq.patch to my openwrt build, to add gpio interrupts to the carambola 2 board (AR9331).
When I export a gpio pin through sysfs, there is no 'edge' file to setup interrupts. A few printks in gpiolib.c showed that it is missing the to_irq function of a gpio_chip struct. I guess I have to add this in the board specific machine file (arch/mips/ath79/mach-carambola2.c) but I can't figure out how.
Could you give me any advice, how to add the interrupt functions correctly to the kernel?
Best.

GPIO interrupt support on ar71xx for infrared RC

I would like to use an infrared remote control receiver (e.g., Vishay TSOP series) on the GPIO lines of ar71xx based boards, which apparently requires GPIO interrupt support.

Can this be done?

Please also see
https://forum.openwrt.org/viewtopic.php?pid=259392

mcp25xxfd pending mask off by one

I am suspecting that the code at line 1908 may have an error.
if (pending_mask)
fifo = fls(pending_mask);
else
fifo = priv->fifos.tx_fifo_start;

/* handle error - this should not happen... */
if (fifo >= priv->fifos.tx_fifo_start + priv->fifos.tx_fifos) {

If i set the bitrate of two can buses to be mismatched I get an expected bus error. However when I reset the rates to match the fifo value gets set to 32 by the if(pending_mask) returning true. I think this is because the fls will return 32 instead of the expected 31. So I think the code should be
fifo = fls(pending_mask) - 1;

If I make this change I no longer get the error and the communication resumes.

However after such an error the pending mask always remains set. I am not sure where the pending mask should get cleared.

fq_codel on can is a bad idea

you should either use noqueue (buffer up 2 packets) or a pfifo on a can bus. openwrt defaults to fq_codel and rips out pfifo_fast entirely.

AR9344 - GPIO interrupt polarity issue

Hi GBert,

I'm using your code regarding ATH79 gpio interrupt system on an AR9344-based board. Connected to GPIO11 I have a chip that gives me time synchronization emitting a square signal with a period of 1 second. I would like to generate an interrupt on each cycle, so I configured GPIO interrupt as IRQ_TYPE_EDGE_RISING.
The problem I'm experimenting is that instead on one interrupt per cycle I get two interrupts each period. The delay between these two interrupts is exactly equal to the time that the square signal stays on the high level (see attached image). This lead me think that for some reason the interrupt is sensible to both the rising and the falling edge.
Have you ever experienced something like that?

Gaetano.

gpio-irq-test in latest openwrt trunk issue

hi GBert,

i`m trying to test gpio-irq-test module in newest openwrt trunk. when i insmod, "gpio_to_irq" always return -6

root@OpenWrt:/lib/modules/4.9.77# insmod gpio-irq-test.ko gpio=10
[ 87.489478] requested GPIO 10
[ 87.492640] can't map GPIO 10 to IRQ : error -6
[ 87.497312] freeing GPIO 10
failed to insert gpio-irq-test.ko

i saw that in older openwrt sourcecode, gpio_to_irq is defined in ath79/gpio.c, :
int gpio_to_irq(unsigned gpio)
{
if (gpio > ath79_gpio_count) {
return -EINVAL;
}

return ATH79_GPIO_IRQ_BASE + gpio;

}
EXPORT_SYMBOL(gpio_to_irq);

but the newest trunk dosen`t have one.

is there a new way to make the gpio irq work?

Thanks

r

using i2s(plus DMA)

Theoretically, are we can use i2s(plus DMA) interface as high speed SPI?
Anyway, what the maximum output frequency-specific PLL(pll_cfg_25MHz or pll_cfg_40MHz or Higher)/DIV(for example, we set DIV=1)/CHANNELS for i2s (in practice)?
for example for SPI-master, need DO(Left or Right channel), DI(Line IN or Microphone), SCLK (Left or Right channel) = its 2 or 4 CHANNELS?

compatibility issue

hello GBert:
I see this i2s driver is for ar934x,and i want to know if this misc driver can be compatible with ar9331 i2s driver?