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A (Py)thon (D)SL for (G)enerating (In)struction set simulators.
License: BSD 3-Clause "New" or "Revised" License
This project forked from cornell-brg/pydgin
A (Py)thon (D)SL for (G)enerating (In)struction set simulators.
License: BSD 3-Clause "New" or "Revised" License
Needs looking up in reference manual.
32 and 16 bit versions of:
IDLE should behave like this:
STATUS[0]=0
while(!ILAT){
PC=PC;
}
i.e. it should wait for an interrupt.
Files in epiphany/test/asm/
need:
The reference manual suggests unimpl
is a 16 bit instructions, but its opcode will not fit in 16 bits!
There is no swi
opcode in the Epiphany ISA, but the trap16
instruction can be used to invoke syscalls.
The Epiphany can count events, such as the number of integer or FP instructions executed. This needs to be added to many instructions. Needs support for interrupts. Will affect COUNTER0
and COUNTER1
registers.
16 and 32 bit versions of:
This will significantly affect the memory model, although the code should be quite simple. All instructions marked LABS
in the reference manual require multicore support. The maximum number of cores in an Epiphany chip is 4095
.
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