frobino / axi_custom_ip_tb Goto Github PK
View Code? Open in Web Editor NEWA testbench for an axi lite custom IP
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tropical-peach ashikpoojari wzab abhinavhimanshu sebo83910 njohnsoncpe-zz dosoon883 steve-b t-aras pemd-sysaxi_custom_ip_tb's Issues
To AXI4 Spec?
Hi there, I'm wondering if this is up to AXI4 spec? I'm working on writing to a BRAM block and the write data is asserted a clock after the address is properly received by the block. In this manual it's on page 15.
In your simulation, the address and write data are asserted at the same time.
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