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UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina

Verilog 64.29% Python 11.97% Tcl 23.74%
arquitectura-de-computadores basys3-fpga computerarchitecture fcefyn hardwaredescription uart unc verilog

alu-uart-basys3's Introduction

Hey! ๐Ÿ‘‹

however you got here..

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I'm a senior computer engineering student with experience in both high-level and low-level software development. I also have knowledge in a wide range of subjects such as electronics, computer architecture, networking, etc.

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๐Ÿ’ผ Software Engineer Intern at Avature.

Things i'm working on ๐Ÿšง

  • Choosing the subject for my thesis.
  • Getting my degree in computer engineering at @FCEFyN, UNC.

Some of my Skills ๐Ÿ‘Œ:

  • GNU Linux distributions.
  • Knowledge of design patterns.
  • Use of VCS (Git and GitHub, GitLab) and CI tools (GitHub Actions, CircleCI).
  • Docker, docker compse. Kubernetes Basics. AWS basics.
  • Knowledge of relational DBMS (MySQL).
  • Losts of other useful stuff i've learned. Check some of my projects below ๐Ÿ‘‡๐Ÿป

alu-uart-basys3's People

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