Comments (1)
On that note, the SSD reference design doesn't even use EXT_SSD2_CLK_REQ and the other SSD-specific pins. So I assume it is truly outdated.
Another question that is wide open is how is the second PCIe port activated then, so that DP AUX is disabled?
Is it controlled over the yet undocumented DDS I2C (Expansion Bay Module control)?
Side note, this is not relevant to me specifically anymore, since it sacrifices the DP AUX pair which seems to be required for DP to work, I opted to use the original REFCLK (and pull CLKREQ down)
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