fpgawars / icestudio Goto Github PK

I am opening an example (or create a new one from scratch). Then when I click on any of the entries of the tool menu, the icestudio is closed and opened again, losing the current circuit.

If I click on upload, The bitstream is generated and upload into the board, but then the icestudio is reset.

I have tested from the develop branch

Using NSIS create a Windows installer during package.

Hi,
I'm unable to connect a input block to the input terminal of a pull-up-inv configuration block. This is happening having the latest code from the repository.
Any chances i'm doing something wrong?
Find the test project attached.

test1.ice.zip

Icestudio version: 0.2.0-beta2-dev
Platform: Ubuntu 16.04

A info block is placed in a blank project. When the verify/build option is pressed, the following error messages appears: main.v:2:error: unkwnown module type: main_basic_info

info-test.ice.zip

Cuando modificas una etiqueta de un bloque, si haces un CTRL+C (por ejemplo, para copiar esa etiqueta), además te hace un clonado del bloque ;)

Lo mismo sucede si estás en un bloque de código, al hacer un CTRL+C te hace un clonado del bloque.

También, cuando estás modificando una etiqueta, si presionas CTRL+SUPR, te muestra la ventana de verificación de borrado del bloque actual.

Mac 10.11.4
ctrl+c, cmd+c, ctrl+v, cmd+v, ctrl+x, cmd+x, ctrl+z

working: cmd+z

On exit: save the selected board in the user's profile. Then, restore this board on start.

By default, al the unkwon labels in a verilog file are defined as wires. This bahaviour is very dangerous. Any typo on the signals name will be not detected.

To solve this, all the verilog files include this command in the beginning:
`default_nettype none

If the tools detect a signal that has not been previously declared, an error will be shown

It very import that icestudio add automatically that statement. It will prevent a lot of hours of debugging

This feature was suggested by Carlos Santiago Díaz in this thread in the FPGAwars group:

https://groups.google.com/d/msg/fpga-wars-explorando-el-lado-libre/lwcM-2Ufejs/I0e9mpHVCAAJ

File > Export to verilog save generated verilog code in a pretty format.

The input-config block is a kind of special block, different than the rest. It only can be used near a input pad and it does not belongs to the digital electronic standard. So I propose to change the background to a different color, to avoid confusions or error (Yesterday I made a mistake joining two of this blocks by mistake, because one of them was inside another block. As they had the same color than standard blocks It took me a while to find the error).

After thinking about it, I realized that the config block are different, and should have a different blackground color.

I propose to use a color near to the yellow of the input pads: a kind of light orange or something similar

0.1-Beta-1

Ubuntu 15.10

When I execute icestudio directly from Nautilus, I get the error "Apio not installed". But if I execute from the command line (in the same directory when is located icestudio) it works ok

It would be great to have parcial implementation of the buses, only for connecting blocks.

Let's take this two blocks as an example, conected by a wire. It is done in icestudio like this:

If it was a bus (8 bits) instead of a wire, the generated code (in human readable verilog code) will be:

`default_nettype none

module main ();


 wire [7:0] w0;  //-- Bus de union

 bloque1 TEST1 (
  .out(w0)
 );

 bloque2 TEST2 (
  .in(w0)
 );
endmodule


//-- Bloque 1: Bus de salida de 8 bits
module bloque1 (output [7:0] out);
 assign out = 8'hFF;

endmodule

//-- Bloque 2: Bus de entrada de 8 bits
module bloque2 (input [7:0] in);
 wire [7:0] temp;

 assign temp = in;


endmodule

This is another example: the connection of 3 blocks:

If it was an 8 bits bus, the generated code should be like this:

`default_nettype none

module main ();

 wire [7:0] w0;
 wire [7:0] w1;

 assign w1 = w0;

 bloque1 v62df90 (
  .out(w0)
 );

 bloque2 v8cd364 (
  .in(w0)
 );

 bloque3 ve05eb2 (
  .in(w1)
 );

endmodule

module bloque1 (output [7:0] out);
 assign out = 8'hFF;

endmodule

module bloque2 (input [7:0] in);
 wire temp;

 assign temp = in;


endmodule

module bloque3 (input [7:0] in);
 wire temp;

 assign temp = in;
endmodule

Restrictions:

• Only buses with the same width can be connected
• Connection between output buses with input buses (no input/output buses yet)

This implementation will let us to include a lot of new circuit in icestudio

I have implemented a 16x8 rom as a code block. Its content is loaded from an external file. When building the project, it does not find the file.

The verilog code is (inside the block):

reg [7:0] rom [0:15];
reg [7:0] data;
wire [3:0] addr;

//-- Name of the file with the rom contents
parameter ROMFILE = "rom2.list";

assign addr = {a3,a2,a1,a0};

always @(negedge clk) begin
  data <= rom[addr];
end

assign {d7,d6,d5,d4,d3,d2,d1,d0} = data;

initial begin
  $readmemh(ROMFILE, rom);
end

This is the icestudio project:

rom16x8-master.ice.zip

Add a translation system contained in each collection. This will be focused on the directory names.

https://docs.google.com/spreadsheets/d/1b0CqJnsPfRYW5v65XKFY7H8DhgSXWPrKbPTp9iEWsLg/edit#gid=0

On OS X 10.12.1 with Icestudio 0.2.3 Beta, enabling drivers caused a complaint that an internet connection is required. I don't have any internet connectivity problems. After reading the install instructions again I installed the most current Python 2.7. Now enabling drivers causes the app to hang.

Add the xor logic gate by Carlos Santiago Díaz, submitted to the FPGAwars list:

https://groups.google.com/d/msg/fpga-wars-explorando-el-lado-libre/FJSynyeprPA/_BqdIeBUDAAJ

It would be great if the user can select more than one modules using a box selecction. It will be very useful for moving many modules at the same time or deleting them

This bug was first observed by Eladio Delgado. He told me the problem and I started to do some test in order to determinate in which part of the stack was originated.

It seems that in some cases the generated Verilog connections are not working ok

I've isolated the problem in this example:

It is a D-flip-flop in which the negated output q_n is connected back to the d input to create a T Flip-flop

The generated verilog code is:

// Code generated by Icestudio 0.3.0-beta3-dev
// Wed, 08 Feb 2017 06:21:21 GMT

`default_nettype none

module main (
 input vd5501f,
 input vclk,
 output v834948,
 output [0:6] vinit
);
 wire w0;
 wire w1;
 wire w2;
 wire w3;
 assign w0 = vd5501f;
 assign v834948 = w1;
 assign w3 = vclk;
 main_v9ef512 v9ef512 (
  .clk(w0),
  .q(w1),
  .q_n(w2)
 );
 assign vinit = 7'b0000000;
endmodule

module main_v9ef512 (
 input d,
 input clk,
 output q,
 output q_n
);
 reg qi = 0;
 always @(posedge clk)
   qi <= d;
 assign q = qi;
 assign q_n = ~qi;
endmodule

We can observe that the d signal is not connected when the module ** main_v9ef512** is instantiated

It should have generated something like this:

main_v9ef512 v9ef512 (
  .clk(w0),
  .q(w1),
  .q_n(w2),
  .d(w2)
 );

(Or using any other temporal wire between q_n and d)

0.1-beta1

Platform: ubuntu 15.10

Examples works ok. But I cannot load external projects previously saves as .json files. It does not generate any error message, just the screen remains blank. No file is loaded

Create a new concept in order to define default configurations in an FPGA board, using a file rules.json in a board directory that contains rules for undefined pins or connections. E.g. All unconnected "clk" ports are connected to CLK pin, if LED0 is not connected it is set to 0.

These smart rules will simplify the design and the setup of the designs.

When opening icestudio-0.3.0-beta-win64 by double clicking on icestudio.exe in Windows 10 x64 (Build 14986), Explorer hangs and icestudio doesn't open.

I have found a work around:
Go to the icestudio-0.3.0-beta-win64 folder open icestudio.exe through powershell

Shortcut from the icestudio-0.3.0-beta-win64 folder:
Alt then F then R
Type: ".\icestudio.exe"

A run command also seems to work:
Windows Key + R
type: "cmd /K C:\icestudio-0.3.0-beta-win64\icestudio.exe"
(replace with your path"

En el archivo patch-iCE40-HX8K.py faltaba la salida D16.
Lo adjunto con la corrección.
patch-iCE40-HX8K.zip

Estoy trabajando con la placa ICE40-HX8K en Windows 8.1 con 64 bits, y no consigo que Icestudio detecte la placa. Instalé los drivers libusbk, como adjunto en una captura, pero no hay forma. Lo he intentado en varios ordenadores con el mismo sistema operativo.

Sin embargo en Ubuntu funciona todo a la primera.

Por otro lado estaría genial que Icestudio aceptara etiquetas para los cables, de forma parecida a como se hace en Altium Designer a la hora de hacer esquemas. Simplificaría mucho todo.

Muchas gracias.

The input of the input-config block can only be connected to an input-pin. It would be great if there appear an error message if the input-config blocks do not meet this requirement

The message could be something like: "Error: The config block's input does not come from an input pin"

When a project is loaded, if its target board is different from the selected board the following options must be shown:

• Load the complete project with its board
• Load the project for the selected board without the FPGA information

When the release zip files is unzip all the files go the current directory.
In my opinion, it would be better include a base "icestudio" directory.

Hi, thanks for the improvements :)
Just updated icestudio from git and when trying to execute it i got the following screen shoot.

Just to ask if somebody have the same results.

Thanks in advance.

If input is connected to a config block, it can not be connected to any other block.

If input is connected to a non config block, it can not be connected to a config block.

• Use "," as separator
• Use multiple textboxes for Input and Output ports in the code blocks

Current method using gui.Window.open generates strange issues:

• If parent windows is removed, new windows can not be properly loaded
• Exploring a child's block changes the parent but not the child
• ...

Then, new Windows must be created using spawn|exec|fork.

In order to open files in childs, Icestudio must capture its args, and load argv[0] as a project:
./icestudio /path/to/project.ice

Add multibit Input and Output blocks.

For example,

1. Add an input block a[7:0].

2. Expand the block to show its combo boxes.

3. Edit the port values and connect the block to a [7:0] input pin.

NW package contains olny 16Mb plus the NW app. It seems that Windows 10 takes too long to unzip this file (performance issue?)

Better wires
Paper pan
Zoom in/out
Multi-select
Edit code block ports
Block size adjustment
More CSS...
Bug z level html elements
Open other menus on hover
Message during Build, Upload until the end

When a block is imported, the //included files must be copied also (.v, .vh and .list)

• If this file does not exist in the orig directory -> message(ok)
• It this file already exists in the dest directory -> message(replace, cancel)

Add an orange block with a pin connection at the bottom. This block contains the name and a textbox field:

 _________
|    x    |
|  _____  |
| |_____| |
|_________|
     |

If the counterAsc and counterDes blocks are used on the user project without the constant blocks they use a default value that i left on the component implementation, in case of using the constant blocks the latter constants are used.

It is better left the implementation like this or change the constants inside the blocks or warn the user that no constants are used at the project level?

Update "ice" project format, version 1.0.0

package
 - name
 - version
 - description
 - author
 - image
design
 - board
 - state
    - pan
    - zoom
 - graph
    - blocks
    - wires
 - dependencies
version

Package section must be set in "Edit > Preferences > Project information".

Also, this project can be "Added as block" in other projects, instead of "Exporting" and "Importing" a block ".iceb". Therefore, ".iceb" format will be deprecated.

The current icestudio window has a fixed size. It cannot be resized or maximized
It would be great if the size can be adjusted

The name of icestudio is oriented for ice40. But is there plan to support other platforms ?
I wonder if it's easy to port icestudio for armadeus platforms apf27 (xilinx spartan3a), apf51 (xilinx spartan6) and apf6_sp (Altera/intel CycloneV) ?
Of course, there is no open-source toolchain to synthetize for it, but maybe we can do somethings to drive close-source tools ?

Adding a context menu for every module. Tipically the context menus are activated by right clilcking. Then context menu should include at least two options:

• delete block
• duplicate block

The idea is to generate graphic blocks with upper pins to connect "Constant" blocks

For example,

1. Add a code block with parameters "N,B"

2. Connect two constant blocks with values 22 and 0 to the code block N and B connections.

3. Export the project as a block

Then all the code blocks are parsed and a "parameters" list generated and included in the block.iceb file.

"parameters": [
  {
    "name": "N",
    "value: "22",
    "default": "22"
  },
  {
    "name": "B",
    "value: "0",
    "default": "0"
  }
] 

4. Import the block.iceb file in a new project

The block appears with the upper pins "N,B".

5. Edit the parameters.

Add and connect two Constant blocks N and B and write the values 23, 1.

6. Save the project

These new values are updated in the project.ice file ("parameters" list).

7. Build the project

The verilog compiler adds the parameters into the corresponding modules.

modtype #(
     .N(23),
     .B(1)) modname (...)

I cannot upload the ACC0 project into the Icezum because it does not build on icestudio 0.2. The steps to reproduce the problem (in my computer) are:

1. I am using icestudio 2.0 installed from the Released package. Execute it
2. Download the ACC0.ice and rom.list files
3. Open the project in Icestudio
4. Click on Tools/Build

The Build start notification appears... and after some seconds, it desappears. No success notification is received.

If the project is exported as verilog (and also the .pcf), it is built correctly with apio build (and apio upload). It works ok in the icezum 1.0

I still do not know if this is a bug, or is something related to my computer. I am testing in ubuntu 16.04-64 bits. I need someone to reproduce it

This issue is related to the Kefir support in apio:

FPGAwars/apio#117