A curated list of amazingly awesome hardware description language projects.
- Verilog IEEE Std 1364-2001, Quick Ref Guide, SystemVerilog 3.1a, Synthesizing SystemVerilog Busting the Myth that SystemVerilog is only for Verification
- VHDL standards IEEE Std 1076-2000
- SystemC standards IEEE Std 1666-2011
- Verilog
- Verilator Verilog to C++ transpiler
- Icarus Verilog - simulator
- Yosys - RTL synthesis
- VHDL
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C/C++
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Haskel
- concat Haskell to hardware, 2016+
- https://github.com/conal/talk-2015-haskell-to-hardware
- CλaSH - A functional hardware description language
- pipelineDSL - A Haskell DSL for describing hardware pipelines
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Java
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JavaScript
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Julia
- Julia-Verilog - a Verilog-generation DSL for Julia., 2017
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Python
- HWT Meta HDL, verification env. IP-core generator, analysis tools, HDL glue
- garnet Coarse-Grained Reconfigurable Architecture generator based on magma, 2018+
- magma - Meta HDL, 2017+
- migen - Meta HDL, 2013+
- MyHDL - Process based HDL, verification framework included, 2004+
- PyRTL - Meta HDL, simulator suitable for research.
- PyMTL - Process based HDL, verification framework included, 2014+
- veriloggen - 2015-?, Python, Verilog centric meta HDL with HLS like features
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Rust
- hoodlum - Meta HDL, 2016+
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Scala
- hlslibs - ac_math, ac_dsp, ac_types
- legup - 2011-2015, LLVM based c->verilog
- bambu - 2003-?, GCC based c->verilog
- augh - c->verilog, DSP support
- https://github.com/utwente-fmt - abstract hls, verification libraries
- Shang - 2012-2014, LLVM based, c->verilog
- xronos - 2012, java, simple HLS
- Potholes - 2012-2014 - polyhedral model preprocessor, Uses Vivado HLS, PET
- hls_recurse - 2015-2016 - conversion of recursive fn. for stackless architectures
- hg_lvl_syn - 2010, ILP, Force Directed scheduler
- abc <2008-?, A System for Sequential Synthesis and Verification
- polyphony - 2015-2017, simple python to hdl
- DelayGraph - 2016, C#, register assignment algorithms
- coreir - 2016-?, LLVM HW compiler## License
- act - asynchronous circuit/compiler tools
- vtr-verilog-to-routing
- yosys - RTL synthesis framework
- bitfield - Javascript bit field diagram renderer
- d3-wave - Javascript wave graph visualizer for RTL simulations
- d3-hwschematic - Javascript hierarchycal schematic visualizer for HDLs
- wavedrom - Javascript wave graph visualizer for documentations and sim.
- netlistsvg - Javascript schematic visualizer
- sphinx-hwt - Plugin for sphinx documentation generator which adds shematic into html documentaion.
- hdlConvertor - Fast (System) Verilog/VHDL parser writen as C++ extension for Python
- pyVHDLParser - VHDL parser written in Python
- rust_hdl - VHDL parser and language server written in Rust
- midas - FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
- cocotb - A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
- opencores.org - webpage which hosts many openhardware projects
- enjoy-digital repositories - Migen, SoC level modules
- ZipCPU repositories - Verilog, mostly peripherals, DSP
- rhea - MyHDL, SoC level modules
- FPGAwars FPGA-peripherals - Verilog, simple peripherals
- PoC - VHDL, utils
- picorv32 - Verilog, A Size-Optimized RISC-V SoC
- openrisc - OpenRISC, FuseSoC, peripherals and cpu parts
- NyuziProcessor - GPGPU
- VexRiscv - RISC-V written in SpinalHDL
- Awesome Open Hardware Verification - A list of open source tools and frameworks for hardware verification.
To the extent possible under law, Aliaksei Chapyzhenka has waived all copyright and related or neighboring rights to this work.