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ebaz4205_fpga's Issues

Ethernet PHY and Zynq generated clock

Your tutorials are great - however there is an improvement you could make.
Many of the EBAZ4205s are now the component optimised version where the clocks to the IP101GA PHY are supplied by the PL side of the Zynq. There's also a need to concat the nibbles that come over the PHY over the GMII interface.

I can make this work using Vivado block design - but hopeless at making it work with your code.

Perhaps you could have a shot?

Running opt_design produces errors on vivado v2020.2

Hello! Love your blog and content you produce! I tried to using Vivado project with v2020.2 version. I'm not sure is that the culprit or missing files in the project but synthesis fails with following errors

...

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 4 threads
ERROR: [DRC INBB-3] Black Box Instances: Cell 'system_wrapper_i/system_i' of type 'system' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port ddr_addr_io[0] expects both input and output buffering but the buffers are incomplete.
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port ddr_addr_io[10] expects both input and output buffering but the buffers are incomplete.
...
INFO: [Project 1-461] DRC finished with 1 Errors, 130 Warnings
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.87 . Memory (MB): peak = 2334.043 ; gain = 31.754 ; free physical = 7005 ; free virtual = 12020
INFO: [Common 17-83] Releasing license: Implementation
12 Infos, 130 Warnings, 1 Critical Warnings and 2 Errors encountered.
opt_design failed
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.
...

And when trying to open the design with Vivado the file looks like this
image

Tried both 2020.1 and main branches and the same result. I new to Vivado tools and FPGA design in general so sorry if this is question that should be obvious.

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