eedesignhouse Goto Github PK

raspberry

raspberry pi3 common module

remusic

仿网易云音乐 安卓版，netease android，音乐播放器 在线 下载

riscv

Verilog implementation of a RISC-V core

riscv-1

RISC-V CPU Core (RV32IM)

riscv-boom

BOOM: Berkeley Out-of-Order Machine

riscv-dv

SV/UVM based instruction generator for RISC-V processor verification

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

rocket-chip

Rocket Chip Generator

scikit-dsp-comm

A collection of functions and classes to support signal processing and communications theory teaching and research

sdrsharp

sdrsharp-plutosdr

ADALM-PLUTO frontend for SDRSharp

serprog-stm32vcp

Please consider the new stm32-vserprog (https://github.com/dword1511/stm32-vserprog) project which uses libopencm3 and compiles with standard gcc-arm-none-eabi toolchain.

sf32u4_boards

Support files for SparkFun's 32u4-based Arduino-compatible development boards.

shadowsocksr

Python port of ShadowsocksR

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

spectrogram

80MHz bandwidth with LimeSDR-Mini and GQRX

ss

I spend many ways to break the GFW,and this is my destination.

stm32f4-bootloader

Download a **.bin to spi flash, and copy it to external sram and run with the command 'bootm'.

sudo_inject

[Linux] Two Privilege Escalation techniques abusing sudo token

superscalar-riscv-cpu

super-scalar out-of-order RV32IMC cpu core,4 DMIPS/MHz(best), 2 DMIPS/MHz(legal)

tcp2tcp

A simple tcp to tcp proxy server.

tensorcomprehensions

A domain specific language to express machine learning workloads.

thesiscode

Code for my thesis project.

tincr

A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite

verilog-axi

Verilog AXI components for FPGA implementation

vexriscv

A FPGA friendly 32 bit RISC-V CPU implementation

vitis-tutorials

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

w7500p

weightagnostic.github.io

repo for interactive article