Coder Social home page Coder Social logo

doudouli12 / alu_verification_ip Goto Github PK

View Code? Open in Web Editor NEW

This project forked from appledore22/alu_verification_ip

0.0 0.0 0.0 241 KB

Verification IP for ALU written using SystemVerilog (UVM)

License: MIT License

SystemVerilog 92.87% Verilog 7.13%

alu_verification_ip's Introduction

ALU_Verification_IP

Verification IP for ALU written using SystemVerilog (UVM)

This Document is organized as follows -

  1. Project Information
  2. Code Information
  3. Usage
  4. Results
  5. References

Project Information

Understanding the flow of data in UVM is pretty confusing. For this project I have used, the below diagram as a reference.

Testbench Arhitecture

The seq item will randomize operands and opcode and send this packet to the driver. The driver puts this data on the interface. The active monitor/passive monitor samples the data from the interface and converts it into a single packet. The scoreboard calculates the expected data from the packet received from the active monitor. It then compares these packet with the packet received from the passive monitor. If both the packets are same then the testcase is successful.

Code Information

  1. Enum is used for different opcodes (see seq_item.sv)

  2. Two testcases are considered for verifiying the DUT -

    1. Random opcodes
    2. Specific opcode

    See alu_test.sv The base class contain alu_test contain methods for UVM_Reporting. This base class is extended into alu_test_random and alu_test_add. The alu_test_random will randomize the opcodes while the alu_test_add will set the opcode to ADD. User can extend this class (alu_test) to create there own test-cases for different opcodes. Also following the UVM Methodology, every testcase is given a separate sequence. See alu_sequence.sv

Usage

For Questasim Users

  1. Copy the repository files in your directory
  2. Open Questasim

Type in the Transcript

  1. cd <your_directory>
  2. vlib my_lib
  3. vmap work my_lib
  4. vlog alu_top.sv
  5. vsim alu_top
  6. run 2000ns

Results

Output for verbosity MEDIUM

References

1.  DUT - https://esrd2014.blogspot.com/p/8-bit-arithmetic-and-logic-unit.html
2.  https://www.edaplayground.com/x/ezS
3.  https://www.chipverify.com/uvm/using-decl-macro-in-tlm
4.  https://www.chipverify.com/uvm/macros-and-defines
5.  https://www.verificationguide.com/p/uvm-tutorial.html

alu_verification_ip's People

Contributors

appledore22 avatar

Recommend Projects

  • React photo React

    A declarative, efficient, and flexible JavaScript library for building user interfaces.

  • Vue.js photo Vue.js

    ๐Ÿ–– Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.

  • Typescript photo Typescript

    TypeScript is a superset of JavaScript that compiles to clean JavaScript output.

  • TensorFlow photo TensorFlow

    An Open Source Machine Learning Framework for Everyone

  • Django photo Django

    The Web framework for perfectionists with deadlines.

  • D3 photo D3

    Bring data to life with SVG, Canvas and HTML. ๐Ÿ“Š๐Ÿ“ˆ๐ŸŽ‰

Recommend Topics

  • javascript

    JavaScript (JS) is a lightweight interpreted programming language with first-class functions.

  • web

    Some thing interesting about web. New door for the world.

  • server

    A server is a program made to process requests and deliver data to clients.

  • Machine learning

    Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.

  • Game

    Some thing interesting about game, make everyone happy.

Recommend Org

  • Facebook photo Facebook

    We are working to build community through open source technology. NB: members must have two-factor auth.

  • Microsoft photo Microsoft

    Open source projects and samples from Microsoft.

  • Google photo Google

    Google โค๏ธ Open Source for everyone.

  • D3 photo D3

    Data-Driven Documents codes.