Verification IP for ALU written using SystemVerilog (UVM)
- Project Information
- Code Information
- Usage
- Results
- References
Understanding the flow of data in UVM is pretty confusing. For this project I have used, the below diagram as a reference.
The seq item will randomize operands and opcode and send this packet to the driver. The driver puts this data on the interface. The active monitor/passive monitor samples the data from the interface and converts it into a single packet. The scoreboard calculates the expected data from the packet received from the active monitor. It then compares these packet with the packet received from the passive monitor. If both the packets are same then the testcase is successful.
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Enum is used for different opcodes (see seq_item.sv)
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Two testcases are considered for verifiying the DUT -
- Random opcodes
- Specific opcode
See alu_test.sv The base class contain alu_test contain methods for UVM_Reporting. This base class is extended into alu_test_random and alu_test_add. The alu_test_random will randomize the opcodes while the alu_test_add will set the opcode to ADD. User can extend this class (alu_test) to create there own test-cases for different opcodes. Also following the UVM Methodology, every testcase is given a separate sequence. See alu_sequence.sv
For Questasim Users
- Copy the repository files in your directory
- Open Questasim
Type in the Transcript
- cd <your_directory>
- vlib my_lib
- vmap work my_lib
- vlog alu_top.sv
- vsim alu_top
- run 2000ns
1. DUT - https://esrd2014.blogspot.com/p/8-bit-arithmetic-and-logic-unit.html
2. https://www.edaplayground.com/x/ezS
3. https://www.chipverify.com/uvm/using-decl-macro-in-tlm
4. https://www.chipverify.com/uvm/macros-and-defines
5. https://www.verificationguide.com/p/uvm-tutorial.html